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11. 发明授权

US08575970B2 Track and hold circuit and related receiving device with track and hold circuit employed therein 有权
标题翻译：跟踪和保持电路及其中使用的跟踪和保持电路的相关接收设备
公开(公告)号：US08575970B2
公开(公告)日：2013-11-05
申请号：US12695164
申请日：2010-01-28
申请人： Hung-Chieh Tsai , Yu-Hsin Lin , Chi-Lun Lo , Jong-Woei Chen
发明人： Hung-Chieh Tsai , Yu-Hsin Lin , Chi-Lun Lo , Jong-Woei Chen
IPC分类号： H03K17/00
CPC分类号： H03G3/3052 , H03G1/0088
摘要： An operational circuit includes: a gain control circuit arranged to provide a gain value upon an input signal according to a set of control signals, wherein the gain control circuit includes a first resistor-based network and a second resistor-based network; an operational amplifier coupled to the gain control circuit and arranged to generate an output signal according to the input signal and the gain value; and a first capacitor coupled to the operational amplifier and arranged to hold the output signal between a first input terminal and a first output terminal of the operational amplifier, wherein when the operational circuit is operating, a first terminal of the first capacitor is consistently coupled to the first input terminal of the operational amplifier, and a second terminal of the first capacitor is consistently coupled to the first output terminal of the operational amplifier.
摘要翻译：运算电路包括：增益控制电路，被配置为根据一组控制信号在输入信号上提供增益值，其中所述增益控制电路包括第一电阻器网络和第二电阻器网络; 运算放大器，耦合到所述增益控制电路并被布置成根据所述输入信号和所述增益值产生输出信号; 以及耦合到所述运算放大器并被布置成将所述输出信号保持在所述运算放大器的第一输入端和所述第一输出端之间的第一电容器，其中当所述运算电路运行时，所述第一电容器的第一端始终耦合到运算放大器的第一输入端和第一电容器的第二端一致地耦合到运算放大器的第一输出端。

12. 发明申请

US20110163612A1 LOAD DEVICES WITH LINEARIZATION TECHNIQUE EMPLOYED THEREIN 审中-公开
标题翻译：使用线性化技术的负载装置
公开(公告)号：US20110163612A1
公开(公告)日：2011-07-07
申请号：US12652041
申请日：2010-01-05
申请人： Jing-Hong Conan Zhan , Jong-Woei Chen
发明人： Jing-Hong Conan Zhan , Jong-Woei Chen
IPC分类号： H02M3/06
CPC分类号： H03H5/12
摘要： A load device has tunable capacitive units including at least a first tunable capacitive unit and a second tunable capacitive unit with different inherent capacitive characteristics, respectively. Each of the first tunable capacitive unit and the second tunable capacitive unit has a first node and a second node, where the first nodes of the first tunable capacitive unit and the second tunable capacitive unit are coupled to a first voltage, the second node of the first tunable capacitive unit is coupled to a second voltage, and the second node of the second tunable capacitive unit is coupled to a third voltage.
摘要翻译：负载装置具有可调电容单元，其包括分别具有不同固有电容特性的至少第一可调电容单元和第二可调谐电容单元。第一可调电容单元和第二可调谐电容单元中的每一个具有第一节点和第二节点，其中第一可调电容单元和第二可调电容单元的第一节点耦合到第一电压，第二节点第一可调电容单元耦合到第二电压，并且第二可调电容单元的第二节点耦合到第三电压。

13. 发明授权

US07759977B1 Buffering circuit 有权
标题翻译：缓冲电路
公开(公告)号：US07759977B1
公开(公告)日：2010-07-20
申请号：US12480669
申请日：2009-06-08
申请人： Hung-Chieh Tsai , Yu-Hsin Lin , Jong-Woei Chen
发明人： Hung-Chieh Tsai , Yu-Hsin Lin , Jong-Woei Chen
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： A buffering circuit includes: a first transistor having a gate terminal coupled to an input signal for buffering the input signal to generate an output signal under an operating current, a second transistor cascoded with the first transistor for generating the operating current for the first transistor according to a control signal at a gate terminal of the second transistor, and a control circuit having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to a reference source. The control circuit adjusts the control signal according to the input signal and the reference source, wherein when a voltage level of the input signal varies, the control circuit is arranged to adjust a voltage level of the control signal such that the adjusted voltage level of the control signal varies inversely proportional to the varied voltage level of the input signal.
摘要翻译：缓冲电路包括：第一晶体管，其具有耦合到输入信号的栅极端子，用于缓冲输入信号以在工作电流下产生输出信号;与第一晶体管级联的第二晶体管，用于产生用于第一晶体管的工作电流，涉及在第二晶体管的栅极端子处的控制信号，以及具有耦合到第一晶体管的栅极端子的第一端子和耦合到参考源的第二端子的控制电路。控制电路根据输入信号和参考源调节控制信号，其中当输入信号的电压电平变化时，控制电路被布置成调节控制信号的电压电平，使得调节的电压电平控制信号与输入信号的变化电压电平成反比变化。

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