专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5818743A Low power multiplier 失效
标题翻译：低功率乘法器
公开(公告)号：US5818743A
公开(公告)日：1998-10-06
申请号：US426349
申请日：1995-04-21
申请人： Wai Lee , Toshiyuki Sakuta
发明人： Wai Lee , Toshiyuki Sakuta
IPC分类号： G06F7/52
CPC分类号： G06F7/5338 , G06F2207/3884
摘要： A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements 70 are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.
摘要翻译：数字乘法器110，用于乘以表示被乘数的多个被乘数信号X0-X23和表示乘法器的多个乘法器信号Y0-Y23。在其中，从乘法器信号和乘法器信号产生多个中间结果信号，例如部分乘积信号。还提供了多个加法器电路40，用于将中间结果信号相加以产生表示乘法和乘法器相乘的结果的多个最终结果信号，其中至少一些加法器电路接收表示中间加法结果的第一信号，至少两个先前的加法器级并且还接收表示作为仅一次加法的结果产生的中间结果的第二信号。最后，将多个延迟元件70放置在所选择的第二信号线中，以便将第二信号的到达延迟到至少一些加法器电路，以便将输入的到达同步到至少一些加法器电路。

12. 发明授权

US5701031A Sealed stacked arrangement of semiconductor devices 失效
标题翻译：密封堆叠布置的半导体器件
公开(公告)号：US5701031A
公开(公告)日：1997-12-23
申请号：US280381
申请日：1994-07-25
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Miyamoto , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： G11C5/00 , H01L23/495 , H01L25/065 , H01L23/28 , H01L23/535 , H01L23/538
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译：一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。堆叠这样连接的DRAM芯片和引线框架的多对，并且引线框架的相应引线共同连接以形成层叠体。这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

13. 发明授权

US5394008A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5394008A
公开(公告)日：1995-02-28
申请号：US84520
申请日：1993-06-30
申请人： Yutaka Ito , Toshiyuki Sakuta , Takumi Nasu
发明人： Yutaka Ito , Toshiyuki Sakuta , Takumi Nasu
IPC分类号： H01L23/12 , H01L23/495 , H01L23/50 , H01L23/64 , H01L23/48 , H01L25/52 , H01L29/44 , H01L29/60
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/647 , H01L24/49 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/06136 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/48624 , H01L2224/49113 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01013 , H01L2924/01015 , H01L2924/01033 , H01L2924/01041 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025
摘要： A semiconductor integrated circuit device with high power noise immunity and high substrate surge immunity. An LOC lead frame to be connected to a power wiring for supplying a source voltage and a ground potential to input circuits of a semiconductor chip is isolated from another LOC lead frame for supplying the source voltage and the ground potential to other circuits. The source voltage and the ground potential for the circuit are supplied by way of external terminals formed by the respective lead frames. Further, the isolated LOC lead frames are connected to each other through a resistive impedance component formed on the semiconductor chip.
摘要翻译：一种半导体集成电路器件，具有高功率噪声抗扰度和高衬底浪涌抗扰度。要连接到用于向半导体芯片的输入电路提供源极电压和接地电位的电源线的LOC引线框架与用于向其他电路提供源极电压和接地电位的另一个LOC引线框架隔离。电路的源极电压和接地电位通过由各个引线框构成的外部端子来提供。此外，隔离的LOC引线框架通过形成在半导体芯片上的电阻阻抗部件彼此连接。

14. 发明授权

US5208782A Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement 失效
标题翻译：具有多个存储块和片上芯片（LOC）布置的半导体集成电路器件
公开(公告)号：US5208782A
公开(公告)日：1993-05-04
申请号：US892708
申请日：1992-05-29
申请人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
发明人： Toshiyuki Sakuta , Masamichi Ishihara , Kazuyuki Miyazawa , Masanori Tazunoki , Hidetoshi Iwai , Hisashi Nakamura , Yasushi Takahashi , Toshio Maeda , Hiromi Matsuura , Ryoichi Hori , Toshio Sasaki , Osamu Sakai , Hiroyuki Uchiyama , Eiji Miyamoto , Kazuyoshi Oshima , Yasuhiro Kasama
IPC分类号： G06F11/18 , G06F11/20 , G11C11/406 , G11C29/00 , H01L27/105 , H01L27/108
CPC分类号： G11C29/808 , G11C11/406 , G11C29/88 , H01L24/06 , H01L27/10805 , G06F11/1666 , G06F11/183 , H01L2224/4826 , H01L27/105 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor integrated circuit memory structure is provided which uses macro-cellulated circuit blocks that can permit a very large storage capability (for example, on the order of 64 Mbits in a DRAM) on a single chip. To achieve, this, a plurality of macro-cellulated memory blocks can be provided, with each of the memory blocks including a memory array as well as additional circuitry such as address selection circuits and input/output circuits. Other peripheral circuits are provided on the chip which are common to the plurality of macro-cell memory blocks. The macro-cell memory blocks themselves can be formed in an array so that their combined storage capacity will form the large overall storage capacity of the chip. The combination of the macro-cell memory blocks and the common peripheral circuitry for controlling the memory blocks permits a faster and more efficient refreshing operation for a DRAM. This is enhanced by a LOC (Lead On Chip) arrangement used in conjunction with the memory blocks.
摘要翻译：提供了一种半导体集成电路存储器结构，其使用宏单元电路块，其可以在单个芯片上允许非常大的存储能力（例如，DRAM中的64Mbits）。为了实现这一点，可以提供多个宏单元存储器块，其中每个存储器块包括存储器阵列以及诸如地址选择电路和输入/输出电路的附加电路。在芯片上提供了多个宏单元存储块通用的其他外围电路。宏单元存储器块本身可以形成为阵列，使得它们的组合存储容量将形成芯片的大的总体存储容量。宏单元存储器块和用于控制存储器块的公共外围电路的组合允许DRAM的更快更有效的刷新操作。这通过与存储器块结合使用的LOC（片上芯片）布置来增强。

15. 发明授权

US4951122A Resin-encapsulated semiconductor device 失效
标题翻译：树脂封装的半导体器件
公开(公告)号：US4951122A
公开(公告)日：1990-08-21
申请号：US199538
申请日：1988-05-27
申请人： Kunihiro Tsubosaki , Gen Murakami , Toshiyuki Sakuta , Masamichi Ishihara , Satoru Ito , Yasuo Mori
发明人： Kunihiro Tsubosaki , Gen Murakami , Toshiyuki Sakuta , Masamichi Ishihara , Satoru Ito , Yasuo Mori
IPC分类号： H01L23/31 , H01L23/495 , H01L23/498
CPC分类号： H01L24/32 , H01L23/3135 , H01L23/49506 , H01L23/4951 , H01L23/49541 , H01L23/49558 , H01L23/49861 , H01L2224/05554 , H01L2224/32014 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/48465 , H01L2224/49175 , H01L2224/73265 , H01L2224/8592 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/1815 , H01L2924/3011 , H01L2924/351
摘要： The present invention relates to a technique in which the pellet fixing parts of a lead frame of the tabless type or the type having no die pads are molded in or coated with a resin beforehand in order to enhance the reliability of a resin-encapsulated IC having become important with enlargement in the size of the chip of a memory IC or the like and reduction in the size of a resin package, and a resin package structure in which the technique of the lead frame having no die pads is applied to flat packaging so as to lessen reflow cracks.
摘要翻译：本发明涉及一种技术，其中预先将无凸型引线框架或不具有模片焊盘的引线框架的芯片固定部件预先模制或涂覆树脂，以提高具有树脂封装的IC的可靠性随着存储器IC等的芯片的尺寸的增大和树脂封装的尺寸的减小而变得重要，并且将没有管芯焊盘的引线框架的技术应用于平面封装的树脂封装结构，因此以减少回流裂纹。

16. 发明授权

US07199472B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07199472B2
公开(公告)日：2007-04-03
申请号：US10970027
申请日：2004-10-22
申请人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
发明人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/5286 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10162 , H01L2924/1306 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB1 of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.
摘要翻译：在由铝构成的最上层布线层和由铜构成的正下方的布线层的半导体装置中，最上层的布线层比其正下方的布线层厚，因此最上层布线层的薄层电阻比接线层正下方。多环电源线VR和焊盘PD由最上层布线层形成，环形电源线VR和焊盘PD分别通过最上层布线层的电力线VLB1连接。因此，可以减小从焊盘PD到环形电源线VR的馈电路径上的电压降，并且可以稳定从焊盘PD到环形电源线VR的电力传导。

17. 发明授权

US06809419B2 Semiconductor device 有权
公开(公告)号：US06809419B2
公开(公告)日：2004-10-26
申请号：US10411118
申请日：2003-04-11
申请人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
发明人： Toshiaki Minami , Toshiyuki Sakuta , Makoto Kuwata
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L23/5286 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/02166 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/4943 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01076 , H01L2924/01079 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10162 , H01L2924/1306 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00
摘要： In a semiconductor device having the upmost wiring layer comprised of aluminum and the wiring layer immediately below it comprised of copper, the upmost wiring layer is made thicker than the wiring layer immediately below it so that the upmost wiring layer is lower in sheet resistance than the wiring layer immediately below it. Multiple ring power lines VR and pads PD are formed of the upmost wiring layer, and the ring power lines VR and the pads PD are connected respectively through power lines VLB1 of the upmost wiring layer. Consequently, the voltage drop on the power feed path from the pads PD to the ring power lines VR can be reduced and the power conduction from the pads PD to the ring power lines VR can be stabilized.

18. 发明授权

US06721774B1 Low power multiplier 失效
标题翻译：低功率乘法器
公开(公告)号：US06721774B1
公开(公告)日：2004-04-13
申请号：US09074197
申请日：1998-05-07
申请人： Wai Lee , Toshiyuki Sakuta
发明人： Wai Lee , Toshiyuki Sakuta
IPC分类号： G06F752
CPC分类号： G06F7/5338 , G06F2207/3884
摘要： A digital multiplier 110 for multiplying a plurality of multiplicand signals X0-X23 representing a multiplicand and a plurality of multiplier signals Y0-Y23 representing a multiplier. In it, a plurality of intermediate results signals, such as partial product signals, are generated from the multiplicand signals and the multiplier signals. A plurality of adder circuits 40 are also provided for adding the intermediate results signals to generate a plurality of final result signals representing the result of multiplying the multiplicand and the multiplier, wherein at least some of the adder circuits receive first signals representing intermediate addition results from at least two prior adder stages and also receive second signals representing intermediate results generated as the result of only a single addition. Finally, a plurality of delay elements 70 are placed in selected second signal lines so as to delay the arrival of the second signals to the at least some of the adder circuits so as to synchronize the arrival of the inputs to the at least some of the adder circuits.
摘要翻译：数字乘法器110，用于乘以表示被乘数的多个被乘数信号X0-X23和表示乘法器的多个乘法器信号Y0-Y23。在其中，从乘法器信号和乘法器信号产生多个中间结果信号，例如部分乘积信号。还提供了多个加法器电路40，用于将中间结果信号相加以产生表示乘法和乘法器相乘的结果的多个最终结果信号，其中至少一些加法器电路接收表示中间加法结果的第一信号，至少两个先前的加法器级并且还接收表示作为仅一次加法的结果产生的中间结果的第二信号。最后，将多个延迟元件70放置在所选择的第二信号线中，以便将第二信号的到达延迟到至少一些加法器电路，以便将输入的到达同步到至少一些加法器电路。

19. 发明授权

US5742101A Semiconductor device 失效
公开(公告)号：US5742101A
公开(公告)日：1998-04-21
申请号：US458166
申请日：1995-06-02
申请人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
发明人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
IPC分类号： H01L23/29 , H01L23/495 , H01L23/48 , H01L23/02 , H01L29/46
CPC分类号： H01L23/4951 , H01L23/293 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48599 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14
摘要： A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.

20. 发明授权

US5365113A Semiconductor device 无效
标题翻译：半导体器件
公开(公告)号：US5365113A
公开(公告)日：1994-11-15
申请号：US125
申请日：1993-01-04
申请人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
发明人： Toshiyuki Sakuta , Kazuyuki Miyazawa , Satoshi Oguchi , Aizo Kaneda , Masao Mitani , Shozo Nakamura , Kunihiko Nishi , Gen Murakami
IPC分类号： H01L23/29 , H01L23/495 , H01L23/48 , H01L23/02 , H01L23/28 , H01L29/46
CPC分类号： H01L23/4951 , H01L23/293 , H01L2224/05599 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48599 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/14
摘要： A semiconductor device is provided in connection with a semiconductor chip which has a plurality of bonding pads at a part corresponding to a centrally located area of the front or first main surface thereof, an organic insulator film which overlies the semiconductor chip and which has an opening in correspondence with the bonding pads, a plurality of leads which overly the organic insulator film, and a molding resin with which these constituents are sealed or packaged.
摘要翻译：半导体器件与半导体芯片相连，该半导体芯片在与其前表面或第一主表面的中心位置相对应的部分处具有多个接合焊盘;半导体芯片，覆盖在半导体芯片上并具有开口与接合焊盘相对应，多个有机绝缘膜上的引线，以及密封或封装这些成分的成型树脂。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式