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11. 发明申请

US20080054413A1 SELF-ALIGNED DUAL SEGMENT LINER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：自对准双分段线束及其制造方法
公开(公告)号：US20080054413A1
公开(公告)日：2008-03-06
申请号：US11468536
申请日：2006-08-30
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L23/58 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/823807 , H01L29/7843
摘要： A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the second liner having a first section covering the first protective layer, a transitional section, and a second section covering the second set of semiconductor devices, the second section being self-aligned to the first liner via the transitional section; forming a second protective layer on top of the second section of the second liner; removing the first section and at least part of the transitional section of the second liner; and obtaining the dual segment liner including the first liner, the transitional section and the second section of the second liner. A semiconductor structure with a self-aligned dual segment liner formed in accordance with one embodiment of the invention is also provided.
摘要翻译：提供一种形成覆盖第一组和第二组半导体器件的双段衬套的方法。该方法包括在其顶部形成第一衬垫和第一保护层，第一衬套覆盖第一组半导体器件; 形成第二衬垫，所述第二衬套具有覆盖所述第一保护层的第一部分，过渡部分和覆盖所述第二组半导体器件的第二部分，所述第二部分经由所述过渡部分自对准到所述第一衬里; 在所述第二衬垫的所述第二部分的顶部上形成第二保护层; 移除所述第二衬套的所述第一部分和所述过渡部分的至少一部分; 并且获得包括第一衬套，第二衬套的过渡部分和第二部分的双段衬管。还提供了根据本发明的一个实施例形成的具有自对准双段衬垫的半导体结构。

12. 发明申请

US20090101979A1 Methods of Forming Field Effect Transistors Having Stress-Inducing Sidewall Insulating Spacers Thereon and Devices Formed Thereby 有权
标题翻译：形成具有应力诱导侧壁绝缘垫片的场效应晶体管的方法和由此形成的器件
公开(公告)号：US20090101979A1
公开(公告)日：2009-04-23
申请号：US11874118
申请日：2007-10-17
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

13. 发明申请

US20080090412A1 Pre-silicide spacer removal 失效
标题翻译：预硅化物间隔物去除
公开(公告)号：US20080090412A1
公开(公告)日：2008-04-17
申请号：US11548842
申请日：2006-10-12
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan , Jun Jung Kim , Yaocheng Liu , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L29/665 , H01L21/32 , H01L29/6653 , H01L29/66545 , H01L29/6659
摘要： A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.
摘要翻译：一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

14. 发明授权

US07482215B2 Self-aligned dual segment liner and method of manufacturing the same 有权
标题翻译：自对准双段衬管及其制造方法
公开(公告)号：US07482215B2
公开(公告)日：2009-01-27
申请号：US11468536
申请日：2006-08-30
申请人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
发明人： Thomas W. Dyer , Sunfei Fang , Jiang Yan
IPC分类号： H01L21/8238 , H01L21/302 , H01L21/461 , H01L21/31 , H01L21/469
CPC分类号： H01L21/76829 , H01L21/823807 , H01L29/7843
摘要： A method of forming a dual segment liner covering a first and a second set of semiconductor devices is provided. The method includes forming a first liner and a first protective layer on top thereof, the first liner covering the first set of semiconductor devices; forming a second liner, the second liner having a first section covering the first protective layer, a transitional section, and a second section covering the second set of semiconductor devices, the second section being self-aligned to the first liner via the transitional section; forming a second protective layer on top of the second section of the second liner; removing the first section and at least part of the transitional section of the second liner; and obtaining the dual segment liner including the first liner, the transitional section and the second section of the second liner. A semiconductor structure with a self-aligned dual segment liner formed in accordance with one embodiment of the invention is also provided.
摘要翻译：提供一种形成覆盖第一组和第二组半导体器件的双段衬套的方法。该方法包括在其顶部形成第一衬垫和第一保护层，第一衬套覆盖第一组半导体器件; 形成第二衬垫，所述第二衬套具有覆盖所述第一保护层的第一部分，过渡部分和覆盖所述第二组半导体器件的第二部分，所述第二部分经由所述过渡部分自对准到所述第一衬里; 在所述第二衬垫的所述第二部分的顶部上形成第二保护层; 移除所述第二衬套的所述第一部分和所述过渡部分的至少一部分; 并且获得包括第一衬套，第二衬套的过渡部分和第二部分的双段衬管。还提供了根据本发明的一个实施例形成的具有自对准双段衬垫的半导体结构。

15. 发明申请

US20080179638A1 GAP FILL FOR UNDERLAPPED DUAL STRESS LINERS 审中-公开
标题翻译：用于下压双重应力衬里的GAP填料
公开(公告)号：US20080179638A1
公开(公告)日：2008-07-31
申请号：US11669287
申请日：2007-01-31
申请人： Thomas W. Dyer , Sunfei Fang
发明人： Thomas W. Dyer , Sunfei Fang
IPC分类号： H01L29/94 , H01L21/336
CPC分类号： H01L21/823425 , H01L21/76801 , H01L21/76829 , H01L21/76832 , H01L21/76837 , H01L21/823807 , H01L21/823864 , H01L29/7843
摘要： A gap fill nitride is formed in an underlapping region between a first semiconductor area with a first stress liner and a second semiconductor area with a second stress liner without plugging other tightly spaced structures. This is achieved by filling the tightly spaced structures with middle-of-line dielectric material such as silicon oxide in both the first and the second semiconductor areas prior to the formation of the gap fill nitride. The combination of the first and second stress liners and the gap fill nitride provides a continuous mobile ion diffusion barrier across the entire surface of a CMOS semiconductor structure.
摘要翻译：在具有第一应力衬垫的第一半导体区域和具有第二应力衬垫的第二半导体区域之间的重叠区域中形成间隙填充氮化物，而不堵塞其他紧密间隔的结构。这是通过在形成间隙填充氮化物之前在第一和第二半导体区域中填充紧密间隔的结构与中间线介电材料（例如氧化硅）来实现的。第一和第二应力衬垫和间隙填充氮化物的组合在CMOS半导体结构的整个表面上提供了连续的移动离子扩散势垒。

16. 发明申请

US20070278585A1 CMOS DEVICES WITH HYBRID CHANNEL ORIENTATIONS, AND METHODS FOR FABRICATING THE SAME USING FACETED EPITAXY 失效
标题翻译：具有混合信道方向的CMOS器件，以及使用面向外延制造其的方法
公开(公告)号：US20070278585A1
公开(公告)日：2007-12-06
申请号：US11422443
申请日：2006-06-06
申请人： Thomas W. Dyer , Sunfei Fang , Judson R. Holt
发明人： Thomas W. Dyer , Sunfei Fang , Judson R. Holt
IPC分类号： H01L29/94
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/1037 , H01L29/78 , H01L29/7853
摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a first set of equivalent crystal planes, and the second device region contains a protruding semiconductor structure having multiple intercepting surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, a first field effect transistor (FET) can be formed at the first device region, which comprises a channel that extends along the substantially planar surface of the first device region. A second, complementary FET can be formed at the second device region, while the second, complementary FET comprises a channel that extends along the multiple intercepting surfaces of the protruding semiconductor structure at the second device region.
摘要翻译：本发明涉及包括至少第一和第二器件区域的半导体衬底。第一器件区域具有沿着第一组等效晶面中的一个取向的基本平坦的表面，并且第二器件区域包含具有沿第二不同组的等效晶面取向的多个截止面的突出半导体结构。可以使用这种半导体衬底形成半导体器件结构。具体地，可以在第一器件区域处形成第一场效应晶体管（FET），该第一器件区域包括沿着第一器件区域的基本平坦的表面延伸的沟道。第二互补FET可以形成在第二器件区域，而第二互补FET包括在第二器件区域沿着突出半导体结构的多个截止表面延伸的沟道。

17. 发明申请

US20110156110A1 Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface Damage 审中-公开
标题翻译：具有栅电极的场效应晶体管具有降低的表面损伤的硅化物层
公开(公告)号：US20110156110A1
公开(公告)日：2011-06-30
申请号：US13043059
申请日：2011-03-08
申请人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
发明人： Jun-jung Kim , Sang-jine Park , Min-ho Lee , Thomas W. Dyer , Sunfei Fang , O-sung Kwon , Johnny Widodo
IPC分类号： H01L29/772
CPC分类号： H01L29/7833 , H01L29/665 , H01L29/6653 , H01L29/7843
摘要： Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.
摘要翻译：形成集成电路器件的方法包括形成具有栅电极的场效应晶体管，栅电极的侧壁上的牺牲隔离物和硅化源/漏区。当形成源极/漏极区域的高掺杂部分时，牺牲间隔物用作注入掩模。然后从栅电极的侧壁去除牺牲隔离物。然后，在栅电极的侧壁上形成应力诱导电绝缘层，其被配置为在场效应晶体管的沟道区域中引起净拉伸应力（用于NMOS晶体管）或压应力（用于PMOS晶体管）。

18. 发明授权

US07488660B2 Extended raised source/drain structure for enhanced contact area and method for forming extended raised source/drain structure 有权
标题翻译：用于增强接触面积的扩展的源极/漏极结构和用于形成延伸的升高的源极/漏极结构的方法
公开(公告)号：US07488660B2
公开(公告)日：2009-02-10
申请号：US11307759
申请日：2006-02-21
申请人： Thomas W. Dyer , Sunfei Fang
发明人： Thomas W. Dyer , Sunfei Fang
IPC分类号： H01L21/336
CPC分类号： H01L21/823814 , H01L21/823418 , H01L21/823425 , H01L21/823475 , H01L21/823871 , H01L29/517 , H01L29/66628 , H01L29/7834
摘要： A semiconductor device comprises a gate electrode stack having sidewalls and a top surface with a gate dielectric layer and the gate electrode, and LDD/LDS regions in the substrate aligned with the stack. Conformal L-shaped etch-stop layers with a thickness from about 50 Å to about 200 Å are formed with a vertical leg on the sidewalls of the stack and a horizontal leg reaching over the LDD/LDS regions next to the stack. RSD regions are formed in contact with the substrate aside from the etch-stop layers. The RSD regions cover the horizontal leg of the etch-stop layer and cover at least a portion of the vertical leg of the etch-stop layer on the sidewall of the gate electrode.
摘要翻译：半导体器件包括具有侧壁的栅极电极堆叠和具有栅极电介质层和栅电极的顶表面，并且衬底中的LDD / LDS区域与堆叠对准。形成厚度为约至约200的保形L形蚀刻停止层，其在堆叠的侧壁上具有垂直支腿，并且在堆叠旁边的LDD / LDS区域上形成水平支线。除了蚀刻停止层之外，RSD区域与基板形成接触。 RSD区域覆盖蚀刻停止层的水平支腿并且覆盖栅电极的侧壁上的蚀刻停止层的垂直支腿的至少一部分。

19. 发明申请

US20080246056A1 SILICIDE FORMATION FOR eSiGe USING SPACER OVERLAPPING eSiGe AND SILICON CHANNEL INTERFACE AND RELATED PFET 审中-公开
标题翻译：使用间隔层叠层的硅化物形成和硅氧烷沟道界面及相关PFET
公开(公告)号：US20080246056A1
公开(公告)日：2008-10-09
申请号：US11697806
申请日：2007-04-09
申请人： Victor W. C. Chan , Thomas W. Dyer , Sunfei Fang , Jinghong Li , Teck J. Tang , Henry K. Utomo , Jiang Yan
发明人： Victor W. C. Chan , Thomas W. Dyer , Sunfei Fang , Jinghong Li , Teck J. Tang , Henry K. Utomo , Jiang Yan
IPC分类号： H01L29/778 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823864 , H01L29/165 , H01L29/495 , H01L29/4966 , H01L29/665 , H01L29/6653 , H01L29/66636 , H01L29/7843
摘要： Methods of forming a suicide in an embedded silicon germanium (eSiGe) source/drain region using a suicide prevention spacer overlapping an interface between the eSiGe and the silicon channel, and a related PFET with an eSiGe source/drain region and a compressive stress liner in close proximity to a silicon channel thereof, are disclosed. In one embodiment, a method includes providing a gate having a nitrogen-containing spacer adjacent thereto and an epitaxially grown silicon germanium (eSiGe) region adjacent to a silicon channel of the gate; removing the nitrogen-containing spacer that does not extend over the interface between the eSiGe source/drain region and the silicon channel; forming a single silicide prevention spacer about the gate, the single silicide prevention spacer overlapping the interface; and forming the silicide in the eSiGe source/drain region using the single silicide prevention spacer to prevent the silicide from forming in at least an extension area of the silicon channel.
摘要翻译：在嵌入式硅锗（eSiGe）源极/漏极区域中使用与eSiGe和硅沟道之间的界面重叠的防止硅化物的衬垫形成硅化物的方法以及具有eSiGe源极/漏极区域和压应力衬垫的相关PFET 公开了其接近硅通道的方式。在一个实施例中，一种方法包括提供具有与其相邻的含氮隔离物的栅极和与栅极的硅沟道相邻的外延生长的硅锗（eSiGe）区域; 去除不在eSiGe源极/漏极区域和硅沟道之间的界面上延伸的含氮隔离物; 在栅极周围形成单个硅化物防止间隔物，单个硅化物防止间隔物与界面重叠; 以及使用单个硅化物防止间隔物在eSiGe源极/漏极区域中形成硅化物，以防止硅化物在硅沟道的至少延伸区域中形成。

20. 发明授权

US07582516B2 CMOS devices with hybrid channel orientations, and methods for fabricating the same using faceted epitaxy 失效
标题翻译：具有混合通道取向的CMOS器件，以及使用分面外延制造其的方法
公开(公告)号：US07582516B2
公开(公告)日：2009-09-01
申请号：US11422443
申请日：2006-06-06
申请人： Thomas W. Dyer , Sunfei Fang , Judson R. Holt
发明人： Thomas W. Dyer , Sunfei Fang , Judson R. Holt
IPC分类号： H01L21/00 , H01L21/76
CPC分类号： H01L29/045 , H01L21/823807 , H01L21/823821 , H01L21/823857 , H01L29/1037 , H01L29/78 , H01L29/7853
摘要： The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a first set of equivalent crystal planes, and the second device region contains a protruding semiconductor structure having multiple intercepting surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, a first field effect transistor (FET) can be formed at the first device region, which comprises a channel that extends along the substantially planar surface of the first device region. A second, complementary FET can be formed at the second device region, while the second, complementary FET comprises a channel that extends along the multiple intercepting surfaces of the protruding semiconductor structure at the second device region.
摘要翻译：本发明涉及包括至少第一和第二器件区域的半导体衬底。第一器件区域具有沿着第一组等效晶面中的一个取向的基本平坦的表面，并且第二器件区域包含具有沿第二不同组的等效晶面取向的多个截止面的突出半导体结构。可以使用这种半导体衬底形成半导体器件结构。具体地，可以在第一器件区域处形成第一场效应晶体管（FET），该第一器件区域包括沿着第一器件区域的基本平坦的表面延伸的沟道。第二互补FET可以形成在第二器件区域，而第二互补FET包括在第二器件区域沿着突出半导体结构的多个截止表面延伸的沟道。

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