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11. 发明申请

US20060128057A1 Xerographic micro-assembler 有权
标题翻译：静电复印机
公开(公告)号：US20060128057A1
公开(公告)日：2006-06-15
申请号：US11011652
申请日：2004-12-14
申请人： Jeng Lu , Eugene Chow
发明人： Jeng Lu , Eugene Chow
IPC分类号： H01L21/50 , H01L21/30 , B23P21/00
CPC分类号： H01L25/50 , H01L21/67271 , H01L21/67282 , H01L21/67294 , H01L24/95 , H01L2224/95085 , H01L2224/95144 , H01L2224/95145 , H01L2924/14 , H01L2924/1461 , Y10T29/4913 , Y10T29/49133 , Y10T29/53004 , Y10T29/5313 , Y10T29/53174 , Y10T29/53178 , Y10T29/53278 , H01L2924/00
摘要： Xerographic micro-assembler systems and methods are disclosed. The systems and methods involve manipulating charge-encoded micro-objects. The charge encoding identifies each micro-object and specifies its orientation for sorting. The micro-objects are sorted in a sorting unit so that they have defined positions and orientations. The sorting unit has the capability of electrostatically and magnetically manipulating the micro-objects based on their select charge encoding. The sorted micro-objects are provided to an image transfer unit. The image transfer unit is adapted to receive the sorted micro-objects, maintain them in their sorted order and orientation, and deliver them to a substrate. Maintaining the sorted order as the micro-objects are delivered to the substrate may be accomplished through the use of an electrostatic image, as is done in xerography. The substrate with the micro-objects is further processed to interconnect the micro-objects—through electrical wiring, for example—to form the final micro-assembly.
摘要翻译：公开了静电印刷微组装系统和方法。系统和方法涉及操纵电荷编码的微物体。电荷编码识别每个微物体并指定其排列方向。微物体在分类单元中排序，使得它们具有定义的位置和取向。分选单元具有基于其选择电荷编码的静电和磁性操纵微物体的能力。分类的微物体被提供给图像传送单元。图像传送单元适于接收分类的微物体，将它们保持在排列顺序和方位，并将其传送到基底。将排序的顺序作为微物体传送到基底可以通过使用静电图像来实现，如在静电复印中所做的那样。具有微物体的衬底被进一步处理以使例如微通孔电线互连，以形成最终的微组件。

12. 发明申请

US20060009051A1 Flexible cable interconnect assembly 有权
公开(公告)号：US20060009051A1
公开(公告)日：2006-01-12
申请号：US11226186
申请日：2005-09-13
申请人： Koenraad Schuylenbergh , Armin Volkel , Thomas DiStefano , Michel Rosa , David Fork , Eugene Chow , Meng Lean
发明人： Koenraad Schuylenbergh , Armin Volkel , Thomas DiStefano , Michel Rosa , David Fork , Eugene Chow , Meng Lean
IPC分类号： H01R12/00
CPC分类号： H01R12/78 , H05K1/147 , H05K3/323 , H05K3/361 , H05K3/365 , H05K2201/044 , H05K2201/09845
摘要： A data transmission interconnect assembly capable of transmission speeds in excess of 40 Gbps in which, for example, a line-card is detachably coupled to a backplane using flexible flat cables that are bent to provide a continuous, smooth curve between the connected boards, and connected by a connection apparatus that employs cable-to-cable interface members that are transparent to the transmitted signal waves. Microspring interface members are formed on the contact structure pressed against the cables to provide interface arrangements that are smaller than a wavelength of the transmitted signal. A connector apparatus uses a cam mechanism to align the cables, and then to press the contact structure, having the microspring interface members formed thereon, against the cables. An alterative contact structure uses anisotropic conductive film.

13. 发明授权

US07884361B2 Pattern-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US07884361B2
公开(公告)日：2011-02-08
申请号：US12817127
申请日：2010-06-16
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L21/00
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

14. 发明申请

US20080089705A1 XEROGRAPHIC MICRO-ASSEMBLER 有权
公开(公告)号：US20080089705A1
公开(公告)日：2008-04-17
申请号：US11959030
申请日：2007-12-18
申请人： Jeng Ping Lu , Eugene Chow
发明人： Jeng Ping Lu , Eugene Chow
IPC分类号： H05K3/32 , G03G15/00
CPC分类号： H01L25/50 , H01L21/67271 , H01L21/67282 , H01L21/67294 , H01L24/95 , H01L2224/95085 , H01L2224/95144 , H01L2224/95145 , H01L2924/14 , H01L2924/1461 , Y10T29/4913 , Y10T29/49133 , Y10T29/53004 , Y10T29/5313 , Y10T29/53174 , Y10T29/53178 , Y10T29/53278 , H01L2924/00
摘要： Xerographic micro-assembler systems and methods are disclosed. The systems and methods involve manipulating charge-encoded micro-objects. The charge encoding identifies each micro-object and specifies its orientation for sorting. The micro-objects are sorted in a sorting unit so that they have defined positions and orientations. The sorting unit has the capability of electrostatically and magnetically manipulating the micro-objects based on their select charge encoding. The sorted micro-objects are provided to an image transfer unit. The image transfer unit is adapted to receive the sorted micro-objects, maintain them in their sorted order and orientation, and deliver them to a substrate. Maintaining the sorted order as the micro-objects are delivered to the substrate may be accomplished through the use of an electrostatic image, as is done in xerography. The substrate with the micro-objects is further processed to interconnect the micro-objects—through electrical wiring, for example—to form the final micro-assembly.
摘要翻译：公开了静电印刷微组装系统和方法。系统和方法涉及操纵电荷编码的微物体。电荷编码识别每个微物体并指定其排列方向。微物体在分类单元中排序，使得它们具有定义的位置和取向。分选单元具有基于其选择电荷编码的静电和磁性操纵微物体的能力。分类的微物体被提供给图像传送单元。图像传送单元适于接收分类的微物体，将它们保持在排列顺序和方位，并将其传送到基底。将排序的顺序作为微物体传送到基底可以通过使用静电图像来实现，如在静电复印中所做的那样。具有微物体的衬底被进一步处理以使例如微通孔电线互连，以形成最终的微组件。

15. 发明申请

US20070158816A1 Contact spring application to semiconductor devices 有权
标题翻译：接触弹簧应用于半导体器件
公开(公告)号：US20070158816A1
公开(公告)日：2007-07-12
申请号：US11331656
申请日：2006-01-12
申请人： Eugene Chow , Christopher Chua , Eric Peeters
发明人： Eugene Chow , Christopher Chua , Eric Peeters
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L24/11 , G01R1/06727 , G01R1/06761 , G01R3/00 , H01L21/568 , H01L21/6835 , H01L23/49811 , H01L24/12 , H01L24/742 , H01L24/81 , H01L2221/68368 , H01L2224/05023 , H01L2224/0508 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/13099 , H01L2224/16 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01022 , H01L2924/01033 , H01L2924/01054 , H01L2924/01082 , H01L2924/14
摘要： A contact spring applicator is provided which includes an applicator substrate, a removable encapsulating layer and a plurality of contact springs embedded in the removable encapsulating layer. The contact springs are positioned such that a bond pad on each contact spring is adjacent to an upper surface of the removable encapsulating layer. The contact spring applicator may also include an applicator substrate, a release layer, a plurality of unreleased contact springs on the release layer and a bond pad at an anchor end of each contact spring. The contact spring applicators apply contact springs to an integrated circuit chip, die or package or to a probe card by aligning the bond pads with bond pad landings on the receiving device. The bond pads are adhered to the bond pad landings. The encapsulating or release layer is then removed to separate the contact springs from the contact spring applicator substrate.
摘要翻译：提供接触弹簧施加器，其包括施加器基板，可移除的封装层和嵌入在可移除封装层中的多个接触弹簧。接触弹簧被定位成使得每个接触弹簧上的接合焊盘与可移除的封装层的上表面相邻。接触弹簧施加器还可以包括施加器基板，释放层，释放层上的多个未释放的接触弹簧和每个接触弹簧的锚固端处的接合垫。接触弹簧施加器通过将接合垫与接收装置上的接合垫平台对准，将接触弹簧施加到集成电路芯片，管芯或封装或探针卡。接合焊盘粘附到接合焊盘平台上。然后去除包封或释放层以将接触弹簧与接触弹簧施加器基板分离。

16. 发明申请

US20070026585A1 Patterned-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US20070026585A1
公开(公告)日：2007-02-01
申请号：US11193847
申请日：2005-07-28
申请人： William Wong , Rene Lujan , Eugene Chow
发明人： William Wong , Rene Lujan , Eugene Chow
IPC分类号： H01L21/84
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

17. 发明申请

US20110163061A1 Method Of Producing Microsprings Having Nanowire Tip Structures 审中-公开
标题翻译：具有纳米线尖端结构的微管生产方法
公开(公告)号：US20110163061A1
公开(公告)日：2011-07-07
申请号：US13044933
申请日：2011-03-10
申请人： Eugene Chow , Pengfei Qi
发明人： Eugene Chow , Pengfei Qi
IPC分类号： C03C25/68 , B05D1/32 , B82Y40/00
CPC分类号： B81C1/0015 , B81B2203/019 , B81B2207/07 , B82Y10/00
摘要： A stress-engineered microspring is formed generally in the plane of a substrate. A nanowire (or equivalently, a nanotube) is formed at the tip thereof, also in the plane of the substrate. Once formed, the length of the nanowire may be defined, for example photolithographically. A sacrificial layer underlying the microspring may then be removed, allowing the engineered stresses in the microspring to cause the structure to bend out of plane, elevating the nanowire off the substrate and out of plane. Use of the nanowire as a contact is thereby provided. The nanowire may be clamped at the tip of the microspring for added robustness. The nanowire may be coated during the formation process to provide additional functionality of the final device.
摘要翻译：应力工程微球通常在基底的平面上形成。纳米线（或等效地，纳米管）也在其顶端形成在基板的平面中。一旦形成，可以例如光刻地限定纳米线的长度。然后可以去除位于微弹簧下面的牺牲层，允许微弹簧中的工程应力使结构弯曲出平面，从而使纳米线离开基底并离开平面。由此提供了使用纳米线作为接触。可以将纳米线夹在微弹簧的末端以增加坚固性。在形成过程中可以涂覆纳米线以提供最终装置的附加功能。

18. 发明申请

US20070221611A1 Method of manufacturing fine features for thin film transistors 有权
标题翻译：制造薄膜晶体管精细特征的方法
公开(公告)号：US20070221611A1
公开(公告)日：2007-09-27
申请号：US11388731
申请日：2006-03-24
申请人： Eugene Chow , William Wong , Michael Chabinyc , Ana Arias
发明人： Eugene Chow , William Wong , Michael Chabinyc , Ana Arias
IPC分类号： H01B13/00 , C23F1/00
CPC分类号： H01L29/4908 , H01L27/124 , H01L27/1292
摘要： A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.
摘要翻译：一种在晶体管上制造诸如小栅电极的精细特征的工艺。该方法涉及一种掩模的喷墨印刷和金属镀层，以在一层中制造亚像素和标准像素尺寸特征。打印创建一个小的子像素大小的间隙掩模，用于电镀精细特征。可以使用第二印刷掩模来保护新形成的栅极并蚀刻连接小栅极的标准像素尺寸线。

19. 发明申请

US20070145523A1 Integrateable capacitors and microcoils and methods of making thereof 审中-公开
标题翻译：可集成电容器和微型线圈及其制造方法
公开(公告)号：US20070145523A1
公开(公告)日：2007-06-28
申请号：US11319056
申请日：2005-12-28
申请人： Eugene Chow , Koenraad Schuylenbergh , David Fork , JengPing Lu
发明人： Eugene Chow , Koenraad Schuylenbergh , David Fork , JengPing Lu
IPC分类号： H01L29/00
CPC分类号： H01G5/18 , B81B3/0051 , H01F17/0006 , H01F17/02 , H01F21/04 , H01F27/40 , H01L28/10 , H01L28/60
摘要： Method for integrally forming high Q tunable capacitors and high Q inductors on a substrate are described. A variable capacitors may employ stops between a moveable electrode and a fixed electrode to reduce and/or prevent electrical shorting between the moveable and fixed electrode. A capacitor may employ a split bottom electrode structure to removing a suspension portion of a moveable top electrode from an RF part of a circuit.
摘要翻译：描述了在衬底上整体形成高Q可调电容器和高Q电感器的方法。可变电容器可以在可移动电极和固定电极之间使用停止以减少和/或防止可移动和固定电极之间的电短路。电容器可以采用分离的底部电极结构来从电路的RF部分去除可移动顶部电极的悬挂部分。

20. 发明申请

US20060065909A1 Selective delamination of thin-films by interface adhesion energy contrasts and thin film transistor devices formed thereby 失效
公开(公告)号：US20060065909A1
公开(公告)日：2006-03-30
申请号：US10950413
申请日：2004-09-28
申请人： William Wong , Chinwen Shih , Rene Lujan , Eugene Chow
发明人： William Wong , Chinwen Shih , Rene Lujan , Eugene Chow
IPC分类号： H01L21/00 , H01L21/84 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L21/20
CPC分类号： H01L29/66765
摘要： Various exemplary embodiments of the systems and methods according to this invention provide for a method of producing a self-aligned thin film transistor, the transistor including a metal layer covering at least a portion of a doped layer, the doped layer covering at least a portion of a dielectric layer, a strain being created in the metal layer, the method includes etching an exposed portion of the doped layer to create a defect at an interface between the doped layer and the dielectric layer so as to initiate a delamination of the doped layer from the dielectric layer. The delamination of the doped layer from the dielectric layer is stopped when the defect propagates into an interface between the doped layer and the dielectric layer that has an adhesive energy that is greater than the strain of the metal layer.

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