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    • 14. 发明授权
    • Apparatus and method for controlling drive of three-phase multiplex
winding motor
    • 用于控制三相多路绕组电机驱动的装置和方法
    • US6107774A
    • 2000-08-22
    • US266588
    • 1999-03-11
    • Tetsuo YamadaTakayuki Mizuno
    • Tetsuo YamadaTakayuki Mizuno
    • H02P27/06H02P21/08H02P25/26H02P5/28
    • H02P21/08H02P25/26
    • In vector control apparatus and method for a three-phase multiplex winding motor, a plurality of inverters are installed, each inverter operatively driving a corresponding one of multiplex windings of the motor and a plurality of inverter controllers are installed whose number corresponds to that of the inverters. Each controller includes: a decoupling voltage calculator for calculating d-axis and q-axis voltage setting values V.sub.1 d* and V.sub.1 q* on the basis of an excitation instruction value Io*, a torque instruction value I.sub.T *, d-axis-and-q-axis current instruction values i.sub.1 d* and i.sub.1 q* which are quotients of the excitation instruction value Io* and the torque instruction value I.sub.T * divided respectively by the multiplex number N of the windings of the motor, and a power supply frequency .omega. which is an addition of a slip frequency .omega.s to a rotor revolution frequency .omega.r; a d-axis-and-q-axis current controller for performing P-I calculations for respective deviations between d-axis current instruction value i.sub.1 d* and its detected value i.sub.1 d and between q-axis current instruction value i.sub.1 q* and its detected value i.sub.1 q so as to derive d-axis and q-axis voltage errors .DELTA.V.sub.1 d and .DELTA.V.sub.1 q ; and a plurality of PWM circuits, each receiving d-axis and q-axis voltages V.sub.1 d and V.sub.1 q as d-axis and d-axis voltage instructions and generating and outputting gate signals to the corresponding one of the inverters, the d-axis and d-axis voltages being respective additions of the d-axis and q-axis voltage setting values V.sub.1 d* and V.sub.1 q* to the d-axis-and-q-axis voltage errors .DELTA.V.sub.1 d and .DELTA.V.sub.1 q.
    • 在用于三相多路复用绕组电动机的矢量控制装置和方法中,安装有多个逆变器,每个逆变器可操作地驱动电动机的相应一个多路绕组,并且安装多个逆变器控制器,其数量对应于 逆变器。 每个控制器包括:去耦电压计算器,用于基于激励指令值Io *,转矩指令值IT *,d轴和q来计算d轴和q轴电压设定值V1d *和V1q * 作为分别由电动机的绕组的多路复用数N划分的激励指令值Io *和转矩指令值IT *的商的电流指令值i1d *和i1q *以及作为电动机的电源频率ω 将转差频率ω加到转子转速ωr上; d轴和q轴电流控制器,用于对d轴电流指令值i1d *和其检测值i1d之间以及q轴电流指令值i1q *和其检测值i1q之间的各个偏差执行PI计算,以便 导出d轴和q轴电压误差DELTA V1d和DELTA V1q; 以及多个PWM电路,其分别接收d轴和q轴电压V1d和V1q作为d轴和d轴电压指令,并将栅极信号产生并输出到相应的一个反相器,d轴和d 轴电压分别是d轴和q轴电压设定值V1d *和V1q *与d轴和q轴电压误差DELTA V1d和DELTA V1q的相加。
    • 15. 发明授权
    • Corrosion resistant electrostatic recording head with multiple layers
    • 耐腐蚀静电记录头,多层
    • US5646669A
    • 1997-07-08
    • US136762
    • 1993-10-15
    • Tetsuo YamadaToshihide TanakaSatoru HirosakiKoji UdagawaYumiko Komori
    • Tetsuo YamadaToshihide TanakaSatoru HirosakiKoji UdagawaYumiko Komori
    • B41J2/415G03G15/05G03G15/32H04N1/032B41J2/41G11B3/00
    • G03G15/323B41J2/415
    • An electrostatic recording head comprises an insulating substrate having a builtup structure thereon. The builtup structure includes, in the following order, a plurality of dielectric electrode strips having portions which are arranged in parallel to and kept away from one another, a first insulating layer, a plurality of discharge electrode strips each extending to intersect with the respective portions of the dielectric electrode strips, a second insulating layer having a plurality of openings to form part of an ion generating space region at individual intersected portions of said discharge electrode strips and said dielectric electrode strips, and a screen electrode which is provided to complete each ion generating space region in association with the second insulating layer and has a plurality of openings, through which ions are passed, corresponding to the respective ion generating space regions. The screen electrode is made of a member which is selected from the group consisting of metals, noble metals and alloys mainly composed of these metals and which has a melting point not lower than 1500.degree. C. Alternatively, the screen electrode may be made of a core member and a surface layer which is made of the above metal member, or an oxidation-resistant material such as an inorganic compound, a polymer or a metal alkoxide polymer.
    • 静电记录头包括其上具有累积结构的绝缘基底。 该组合结构按以下顺序包括多个电介质电极条,它们具有彼此平行并彼此远离配置的部分,第一绝缘层,多个放电电极条,各自延伸以与各部分相交 的第二绝缘层,具有多个开口以在所述放电电极条和所述介电电极条的各个交叉部分处形成离子产生空间区的一部分的第二绝缘层,以及提供以完成每个离子的屏幕电极 产生与第二绝缘层相关联的空间区域,并且具有对应于各个离子产生空间区域的离子通过的多个开口。 屏幕电极由选自金属,贵金属和主要由这些金属组成的合金组成的组中制成,熔点不低于1500℃。或者,屏电极可以由 芯部件和由上述金属构件制成的表面层,或抗氧化材料如无机化合物,聚合物或金属醇盐聚合物。
    • 18. 发明授权
    • Charge detection circuit
    • 充电检测电路
    • US5247554A
    • 1993-09-21
    • US462860
    • 1990-01-05
    • Tetsuo Yamada
    • Tetsuo Yamada
    • G11C19/28G11C27/04H01L29/768
    • G11C27/04G11C19/285H01L29/76816
    • A charge detection circuit includes a p-type semiconductor substrate, a reference voltage source for generating a reference voltage having a predetermined voltage difference with respect to the potential of the semiconductor substrate, a first n.sup.+ -type semiconductor region formed in the semiconductor substrate, for storing a carrier packet, a second n.sup.+ -type semiconductor region formed in the semiconductor substrate and connected to the reference voltage source so as to be kept at a potential substantially equal to the reference potential, an MIS type transfer gate having a channel formed between the first and second semiconductor regions, and a gate electrode insulatively formed over the channel to transfer the carrier packet from the first semiconductor region to the second semiconductor region, a potential detection circuit for detecting the potential of the first semiconductor region, which potential is determined by the amount of carriers in the carrier packet, a signal supply section for supplying a control potential signal to the gate electrode, to control the conduction state of the transfer gate, and a biasing circuit for biasing the potential of the gate electrode according to a preset offset potential. The biasing circuit has a resistor of high resistance connected between the reference voltage source and the gate electrode, to derive the preset offset potential from the reference potential.
    • 电荷检测电路包括p型半导体衬底,用于产生相对于半导体衬底的电位具有预定电压差的参考电压的参考电压源,形成在半导体衬底中的第一n +型半导体区域,用于 存储形成在所述半导体衬底中并连接到所述参考电压源以便保持在与所述参考电位基本相等的电位的第二n +型半导体区域,所述第二n +型半导体区域具有形成在所述基准电压源 第一半导体区域和第二半导体区域以及绝缘地形成在沟道上以将载流子包从第一半导体区域传输到第二半导体区域的栅电极,用于检测第一半导体区域的电位的电势检测电路,该电位由 载波数据包中的载波数量,信号供应部分 用于向栅电极提供控制电位信号,以控制传输栅极的导通状态;以及偏置电路,用于根据预置的偏置电位偏置栅电极的电位。 偏置电路具有连接在参考电压源和栅电极之间的高电阻电阻,以从参考电位导出预设的偏置电位。
    • 19. 发明授权
    • Layer-built solid state image sensing device
    • 层状固态图像感测装置
    • US5170236A
    • 1992-12-08
    • US877214
    • 1992-05-01
    • Tetsuo Yamada
    • Tetsuo Yamada
    • H01L27/146
    • H01L27/14643
    • Disclosed is a layer-built solid state image sensing device comprising: a first semiconductor layer of a first conductivity type; a plurality of optoelectro transducing storage elements having a first optoelectro transduction layer of a second conductivity type opposite to the first conductivity type selectively formed within regions isolated pixel column by pixel column by a first isolating layer of the first conductivity type on the first semiconductor layer surface of the first conductivity type; charge transfer elements having a first impurity layer of the second conductivity type formed in columns a regular distance away from optoelectro transducing storage element columns within the isolating areas on the first semiconductor layer surface, and a transfer conductive electrode layer buried within an insulating film selectively formed on the surface other than the first optoelectro transducing layer and a light shielding electrode provided to enclose the transfer electrode also buried within the insulating film, for reading signal charges stored in the optoelectro transducing storage elements; a second optoelectro transducing layer of the second conductivity type formed on the insulating film and connected to the first optoelectro transducing layer; and a second impurity layer of the first conductivity type for covering the surface of the second optoelectro transducing layer.