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11. 发明授权

US08223542B2 Method of reading data in semiconductor memory device with charge accumulation layer 有权
标题翻译：在具有电荷累积层的半导体存储器件中读取数据的方法
公开(公告)号：US08223542B2
公开(公告)日：2012-07-17
申请号：US12852028
申请日：2010-08-06
申请人： Teruo Takagiwa
发明人： Teruo Takagiwa
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/0483 , G11C2211/5646
摘要： According to one embodiment, a method of reading data in a semiconductor memory device including a plurality of memory cells associated with rows and columns and a plurality of latch circuits associated with the columns includes reading flag data from the memory cells associated with one of the columns into associated one of the latch circuits, selecting one of the latch circuits sequentially, while shifting one of the latch circuits to be selected, and reading the flag data from one of the latch circuits selected in an Nth one of the shifts. N is an integer not less than 0).
摘要翻译：根据一个实施例，一种在包括与行和列相关联的多个存储单元以及与列相关联的多个锁存电路的半导体存储器件中读取数据的方法包括从与列之一相关联的存储单元读取标志数据进入关联的一个锁存电路，同时顺序地选择一个锁存电路，同时移动要选择的一个锁存电路，并从在第N个移位中选择的锁存电路之一读取标志数据。 N是不小于0的整数）。

12. 发明申请

US20100302847A1 MULTI-LEVEL NAND FLASH MEMORY 审中-公开
标题翻译：多级NAND闪存
公开(公告)号：US20100302847A1
公开(公告)日：2010-12-02
申请号：US12791519
申请日：2010-06-01
申请人： Hiromitsu Komai , Teruo Takagiwa
发明人： Hiromitsu Komai , Teruo Takagiwa
IPC分类号： G11C16/04 , G11C7/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C29/846 , G11C2211/5646 , G11C2211/5647
摘要： According to one embodiment, a multi-level NAND flash memory executes a writing of an upper data to a LM flag. When an address of a flag assigns a bad column, a data transfer control circuit and a address control circuit control a write operation of upper data in the flag by an operation of transmitting the upper data of the flag from the bad column data hold circuit to the data latch circuit, reading the lower data of the flag from a redundancy column storing the flag into the data latch circuit, generating an address of a redundancy column storing the flag based on the address of the flag, and forcefully inverting the lower data of the flag in the data latch circuit by using the address of the redundancy column storing the flag.
摘要翻译：根据一个实施例，多级NAND闪速存储器执行将高数据写入LM标志的写入。当标志的地址分配不良列时，数据传送控制电路和地址控制电路通过将标志的高位数据从坏列数据保持电路传送到数据锁存电路，从存储该标志的冗余列读取标志的较低数据到数据锁存电路中，根据标志的地址产生存储该标志的冗余列的地址，并强制反转通过使用存储该标志的冗余列的地址在数据锁存电路中的标志。

13. 发明授权

US06501702B2 Semiconductor memory integrated circuit 失效
标题翻译：半导体存储器集成电路
公开(公告)号：US06501702B2
公开(公告)日：2002-12-31
申请号：US09866065
申请日：2001-05-25
申请人： Teruo Takagiwa , Masami Masuda
发明人： Teruo Takagiwa , Masami Masuda
IPC分类号： G11C300
CPC分类号： G11C29/832 , G11C8/06 , G11C8/10 , G11C29/781
摘要： An address buffer includes a latch circuit, and is controlled by an internal clock signal sent from a clock buffer. A decoding circuit section for selecting a word line is formed of a predecoder and a row decoder for further decoding a decoded output from the predecoder. The predecoder has no latching function, and the row decoder has a latch circuit. A pulse generating circuit generates two timing pulses based on a clock signal CK1. The activation of the row decoder is controlled by the two timing pulses.
摘要翻译：地址缓冲器包括一个锁存电路，由一个从时钟缓冲器发送的内部时钟信号控制。用于选择字线的解码电路部分由预解码器和行解码器形成，用于进一步解码来自预解码器的解码输出。预解码器没有锁存功能，行解码器具有锁存电路。脉冲发生电路基于时钟信号CK1产生两个定时脉冲。行解码器的激活由两个定时脉冲控制。

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