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11. 发明授权

US5047359A Method of implanting into the sidewall of a trench by rotating the wafer 失效
标题翻译：通过旋转晶片将其注入到沟槽的侧壁中的方法
公开(公告)号：US5047359A
公开(公告)日：1991-09-10
申请号：US342673
申请日：1989-04-26
申请人： Masao Nagatomo
发明人： Masao Nagatomo
IPC分类号： H01L21/76 , H01L21/265
CPC分类号： H01L21/26586
摘要： The present invention relates to a method of manufacturing a semiconductor device. In order to controllably introduce impurities into the side wall of a trench 2a by ion implantation impurity ions are directed at a predetermined angle into the side wall of the trench 2a provided in a wafer 2a and, for implantation thereof, at the same time, the wafer 2 is rotated around an ion implantation axis at a rotational speed related to the ion implantation current.
摘要翻译：本发明涉及半导体器件的制造方法。为了通过离子注入将杂质可控地引入沟槽2a的侧壁中，杂质离子以预定角度被引导到设置在晶片2a中的沟槽2a的侧壁中，并且为了植入它们，同时，晶片2以与离子注入电流相关的旋转速度绕离子注入轴旋转。

12. 发明授权

US4333226A Method of forming patterned refractory metal films by selective oxygen implant and sublimation 失效
$Method of forming patterned refractory metal films by selective oxygen implant and sublimation$
标题翻译：通过选择性氧注入和升华形成图案化的难熔金属膜的方法
公开(公告)号：US4333226A
公开(公告)日：1982-06-08
申请号：US209889
申请日：1980-11-24
申请人： Haruhiko Abe , Masao Nagatomo , Natsuro Tsubouchi , Hiroshi Harada , Junichi Mitsuhashi
发明人： Haruhiko Abe , Masao Nagatomo , Natsuro Tsubouchi , Hiroshi Harada , Junichi Mitsuhashi
IPC分类号： H01L21/3213 , H01L21/28 , H01L21/316 , H01L21/321 , H01L21/768 , B05D3/06 , B05D5/12 , H01L21/312
CPC分类号： H01L21/76888 , H01L21/31683 , H01L21/321 , Y10S148/02 , Y10S148/117 , Y10S438/911
摘要： A thin film of a metal which is capable of oxidation and sublimation is formed on a major surface of a semiconductor substrate, and a portion of a major surface of the thin metallic film is irradiated with an oxygen ion beam to convert a portion of the thin metallic film to an oxide, and subsequently the thin metallic film is heat treated to remove the oxide by sublimation, whereby electrodes or wiring for a semiconductor integrated circuit are formed by the remaining thin metallic film.
摘要翻译：在半导体衬底的主表面上形成能够氧化和升华的金属薄膜，并且用氧离子束照射薄金属膜的主表面的一部分，以将薄的一部分金属膜与氧化物接触，随后通过升华来对金属薄膜进行热处理以除去氧化物，由剩余的薄金属膜形成用于半导体集成电路的电极或布线。

13. 发明授权

US4905068A Semiconductor device having interconnection layers of T-shape cross section 失效
标题翻译：具有T形横截面的互连层的半导体器件
公开(公告)号：US4905068A
公开(公告)日：1990-02-27
申请号：US143400
申请日：1988-01-13
申请人： Shinichi Satoh , Makoto Hirayama , Masao Nagatomo , Ikuo Ogoh , Yoshikazu Ohno , Masato Fujinaga
发明人： Shinichi Satoh , Makoto Hirayama , Masao Nagatomo , Ikuo Ogoh , Yoshikazu Ohno , Masato Fujinaga
IPC分类号： H01L21/3205 , H01L21/8242 , H01L23/52 , H01L23/522 , H01L27/10 , H01L27/108
CPC分类号： H01L23/5222 , H01L2924/0002
摘要： A cell plate (6) is formed on a main surface of a semiconductor substrate (7) with an insulating film (8) interposed therebetween and an interconnection (1) having T-shape cross section is formed on the cell plate (6) with an interlayer insulating film (11) interposed therebetween. An upper insulating film (12) is formed to cover the interconnection (1).
摘要翻译：在半导体衬底（7）的主表面上形成有绝缘膜（8）的电池板（6），并且在电池板（6）上形成具有T形横截面的互连（1）夹在其间的层间绝缘膜（11）。形成上绝缘膜（12）以覆盖互连（1）。

14. 发明授权

US5888851A Method of manufacturing a semiconductor device having a circuit portion and redundant circuit portion coupled through a meltable connection 失效
标题翻译：制造具有电路部分的半导体器件的方法和通过可熔连接耦合的冗余电路部分
公开(公告)号：US5888851A
公开(公告)日：1999-03-30
申请号：US74517
申请日：1993-06-11
申请人： Kaoru Motonami , Masao Nagatomo
发明人： Kaoru Motonami , Masao Nagatomo
IPC分类号： H01L21/66 , H01L23/525 , H01L23/528 , H01L29/34
CPC分类号： H01L22/22 , H01L23/5258 , H01L23/5283 , H01L2924/0002
摘要： A semiconductor device includes a specific circuit portion having a predetermined function and a spare redundant circuit portion having the same function as the specific circuit portion. The semiconductor device includes a silicon substrate (1), an interlayer insulating film (2), an LT fuse (3), interconnection layers (4), a testing electrode (5) and a protection film (6). The interlayer insulating film (2) has a groove (11) and is formed on the silicon substrate (1). The LT fuse (3) is formed of polysilicon and is located immediately below the bottom wall of the groove (11). The interconnection layers (4) are formed on the interlayer insulating film (2) with the groove (11) therebetween. The testing electrode (5) is spaced from the interconnection layers (4) and is formed on the interlayer insulating film (2). The protection film (6) is formed on the interlayer insulating film to cover surfaces of the interconnection layers (4) and expose a surface of the testing electrode (5). A laser beam is irradiated to a bottom wall of the groove (11) to fuse and remove a part of the LT fuse (3). This substitutes the specific part having a defect with the redundant circuit portion. In this operation, neither the interconnection layers (4) is damaged, nor short-circuit and breakage thereof are caused.
摘要翻译：半导体器件包括具有预定功能的特定电路部分和具有与特定电路部分相同功能的备用冗余电路部分。半导体器件包括硅衬底（1），层间绝缘膜（2），LT熔丝（3），互连层（4），测试电极（5）和保护膜（6）。层间绝缘膜（2）具有凹槽（11）并形成在硅衬底（1）上。 LT熔丝（3）由多晶硅形成，并且位于槽（11）的底壁的正下方。互连层（4）形成在层间绝缘膜（2）上，其间具有槽（11）。测试电极（5）与互连层（4）间隔开，并形成在层间绝缘膜（2）上。保护膜（6）形成在层间绝缘膜上以覆盖互连层（4）的表面并暴露测试电极（5）的表面。激光束照射到凹槽（11）的底壁，以熔化和去除LT熔丝（3）的一部分。这用具有冗余电路部分的具有缺陷的特定部分代替。在这种操作中，互连层（4）都不会损坏，也不会导致短路和断线。

15. 发明授权

US5241212A Semiconductor device having a redundant circuit portion and a manufacturing method of the same 失效
标题翻译：具有冗余电路部分的半导体器件及其制造方法
公开(公告)号：US5241212A
公开(公告)日：1993-08-31
申请号：US994436
申请日：1992-12-21
申请人： Kaoru Motonami , Masao Nagatomo
发明人： Kaoru Motonami , Masao Nagatomo
IPC分类号： H01L21/66 , H01L23/525 , H01L23/528
CPC分类号： H01L22/22 , H01L23/5258 , H01L23/5283 , H01L2924/0002
摘要： A semiconductor device includes a specific circuit portion having a predetermined function and a spare redundant circuit portion having the same function as the specific circuit portion. The semiconductor device includes a silicon substrate (1), an interlayer insulating film (2), an LT fuse (3), interconnection layers (4), a testing electrode (5) and a protection film (6). The interlayer insulating film (2) has a groove (11) and is formed on the silicon substrate (1). The LT fuse (3) is formed of polysilicon and is located immediately below the bottom wall of the groove (11). The interconnection layers (4) are formed on the interlayer insulating film (2) with the groove (11) therebetween. The testing electrode (5) is spaced from the interconnection layers (4) and is formed on the interlayer insulating film (2). The protection film (6) is formed on the interlayer insulating film to cover surfaces of the interconnection layers (4) and expose a surface of the testing electrode (5). A laser beam is irradiated to a bottom wall of the groove (11) to fuse and remove a part of the LT fuse (3). This substitutes the specific part having a defect with the redundant circuit portion. In this operation, neither the interconnection layers (4) is damaged, nor short-circuit and breakage thereof are caused.
摘要翻译：半导体器件包括具有预定功能的特定电路部分和具有与特定电路部分相同功能的备用冗余电路部分。半导体器件包括硅衬底（1），层间绝缘膜（2），LT熔丝（3），互连层（4），测试电极（5）和保护膜（6）。层间绝缘膜（2）具有凹槽（11）并形成在硅衬底（1）上。 LT熔丝（3）由多晶硅形成，并且位于槽（11）的底壁的正下方。互连层（4）形成在层间绝缘膜（2）上，其间具有槽（11）。测试电极（5）与互连层（4）间隔开，并形成在层间绝缘膜（2）上。保护膜（6）形成在层间绝缘膜上以覆盖互连层（4）的表面并暴露测试电极（5）的表面。激光束照射到凹槽（11）的底壁，以熔化和去除LT熔丝（3）的一部分。这用具有冗余电路部分的具有缺陷的特定部分代替。在这种操作中，互连层（4）都不会损坏，也不会导致短路和断线。

16. 发明授权

US4702796A Method for fabricting a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US4702796A
公开(公告)日：1987-10-27
申请号：US931583
申请日：1986-11-14
申请人： Masayuki Nakajima , Shinichi Sato , Akira Tokui , Akira Kawai , Masao Nagatomo , Hiroji Ozaki
发明人： Masayuki Nakajima , Shinichi Sato , Akira Tokui , Akira Kawai , Masao Nagatomo , Hiroji Ozaki
IPC分类号： H01L21/74 , H01L21/8242 , H01L23/556 , H01L21/04 , B44C1/22 , H01L21/22 , H01L21/306
CPC分类号： H01L27/10844 , H01L21/74 , H01L23/556 , H01L2224/16245 , H01L2224/48247 , Y10S438/965
摘要： The present invention is a method for fabricating a semiconductor device, wherein impurity is selectively diffused to surround a region (7) of a second conductivity type as a bit line formed on a semiconductor substrate (1), thereby forming an impurity diffused region (9) of a first conductivity type having high density and, by extending the impurity diffused region (9) in the element separating step to form a high density region of the first conductivity type having high density.
摘要翻译：本发明是一种制造半导体器件的方法，其中杂质被选择性扩散以包围形成在半导体衬底（1）上的位线的第二导电类型的区域（7），从而形成杂质扩散区域（9 ），并且通过在元件分离步骤中扩展杂质扩散区域（9）以形成具有高密度的第一导电类型的高密度区域。

17. 发明授权

US4956310A Semiconductor memory device and fabricating method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US4956310A
公开(公告)日：1990-09-11
申请号：US195672
申请日：1988-10-05
申请人： Akira Tokui , Shinichi Sato , Akira Kawai , Masayuki Nakajima , Hiroji Ozaki , Masao Nagatomo
发明人： Akira Tokui , Shinichi Sato , Akira Kawai , Masayuki Nakajima , Hiroji Ozaki , Masao Nagatomo
IPC分类号： H01L27/10 , G11C11/34 , H01L21/74 , H01L21/8242 , H01L27/108 , H01L29/08 , H01L29/10
CPC分类号： H01L27/10844 , H01L21/74 , H01L27/10805 , H01L29/0847 , H01L29/1083
摘要： A semiconductor memory device in accordance with the present invention comprises: a semiconductor substrate (1) of a first conductivity type; a charge storage region (6) and a bit line region (7) of a second conductivity type formed on a main surface of the substrate; highly doped regions (12a, 12b) of the first conductivity type formed respectively contiguous to only the bottom boundaries of the charge storage region (6) and the bit line region (7).
摘要翻译：根据本发明的半导体存储器件包括：第一导电类型的半导体衬底（1）; 形成在基板的主表面上的第二导电类型的电荷存储区域（6）和位线区域（7）第一导电类型的高掺杂区域（12a，12b）分别形成为仅与电荷存储区域（6）和位线区域（7）的底部边界邻接。

18. 发明授权

US4341616A Dry etching device 失效
标题翻译：干蚀刻装置
公开(公告)号：US4341616A
公开(公告)日：1982-07-27
申请号：US215185
申请日：1980-12-11
申请人： Masao Nagatomo , Haruhiko Abe , Kazuo Mizuguchi
发明人： Masao Nagatomo , Haruhiko Abe , Kazuo Mizuguchi
IPC分类号： C23F4/00 , H01J37/32 , H01L21/302 , H01L21/3065 , C23C15/00 , C23F1/00
CPC分类号： H01J37/32091 , H01J37/32559
摘要： A dry etching device is provided in which on at least one portion of the path of etchant movement from the plasma production region to the etching workpiece a resin coating containing atoms or molecules of the same type as the chemically active atoms or molecules which constitute the etchant, is formed.
摘要翻译：提供一种干蚀刻装置，其中在腐蚀剂路径的至少一部分从等离子体生成区域移动到蚀刻工件时，树脂涂层含有与构成蚀刻剂的化学活性原子或分子相同类型的原子或分子，形成了。

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