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11. 发明授权

US07373456B2 Disk array apparatus and disk array apparatus controlling method 有权
标题翻译：磁盘阵列装置和磁盘阵列装置控制方法
公开(公告)号：US07373456B2
公开(公告)日：2008-05-13
申请号：US11604216
申请日：2006-11-27
申请人： Takashi Yamazaki , Kazuo Hakamata , Azuma Kano
发明人： Takashi Yamazaki , Kazuo Hakamata , Azuma Kano
IPC分类号： G06F12/00
CPC分类号： G06F3/0625 , G06F1/3221 , G06F1/3268 , G06F3/0634 , G06F3/0653 , G06F3/0659 , G06F3/0689 , G06F11/1662 , G06F11/2094 , G06F11/2097 , G11B19/00 , Y02D10/154 , Y02D50/20
摘要： Times at which requests for a data read or data write from/to a logical volume are received are stored in memory as access times of a RAID group making up the logical volume. When a predetermined time has elapsed after the access time, a number of the hard disk drives according to the redundancy of the RAID group are set to a power saving mode. Assume there are first hard disk drives and second hard disk drives having shorter lifes and the RAID group exceeds a predetermined time after the access time. When the RAID group consists of only the first drives, a number of the first drives according to the redundancy of the RAID group are set to a power saving mode and when it consists of only the second drives, an arbitrary number of second drives are set to a power saving mode.
摘要翻译：接收来自/向逻辑卷的数据读取或数据写入的请求的时间作为构成逻辑卷的RAID组的访问时间被存储在存储器中。当在访问时间之后经过预定时间时，根据RAID组的冗余将多个硬盘驱动器设置为省电模式。假设有第一个硬盘驱动器和第二个硬盘驱动器具有较短的寿命，并且RAID组在访问时间之后超过预定时间。当RAID组仅由第一个驱动器组成时，根据RAID组的冗余将多个第一个驱动器设置为省电模式，并且当仅由第二个驱动器组成时，将设置任意数量的第二个驱动器进入省电模式。

12. 发明授权

US07005998B2 Malfunction-detection method during die clamping step in injection molding machines 有权
标题翻译：注塑机模具夹紧步骤中的故障检测方法
公开(公告)号：US07005998B2
公开(公告)日：2006-02-28
申请号：US11103557
申请日：2005-04-12
申请人： Takashi Yamazaki , Haruyuki Matsubayashi , Takeshi Abe
发明人： Takashi Yamazaki , Haruyuki Matsubayashi , Takeshi Abe
IPC分类号： G08B21/00
CPC分类号： B29C45/844 , B29C45/32 , B29C45/33 , B29C45/7653 , B29C45/768 , B29C2045/1792 , B29C2945/76006 , B29C2945/76013 , B29C2945/7602 , B29C2945/76083 , B29C2945/76163 , B29C2945/76173 , B29C2945/76224 , B29C2945/76227 , B29C2945/76257 , B29C2945/76307 , B29C2945/76391 , B29C2945/76498 , B29C2945/76505 , B29C2945/76785 , B29C2945/76913 , B29C2945/76943 , B29C2945/76973
摘要： The present invention relates to a method of detecting a malfunction during a die clamping step in an injection molding machine. A reference pattern is taken which shows a relation between a die clamping force and a position of a movable platen when die clamping is normally carried out. One or more monitoring sections are set in advance with respect to that position on the basis of the reference pattern and an allowable limit value of a die clamping force in the respective monitoring sections is also set in advance in a form of a linear function of the position. The die clamping force is monitored in the respective monitoring section during a respective die clamping step and, when its value exceeds the allowable limit value, it is decided that a malfunction occurs and an alarm is issued.
摘要翻译：本发明涉及一种在注射成型机中检测模具夹紧步骤期间的故障的方法。示出了当正常进行模具夹紧时，模具夹紧力与可动压板的位置之间的关系的参考模式。基于参考图案相对于该位置预先设置一个或多个监视部分，并且预先在各监视部分中的模具夹紧力的允许极限值以位置。在相应的模具夹紧步骤期间，在相应的监视部分中监视模具夹紧力，并且当其值超过允许极限值时，确定发生故障并发出报警。

13. 发明授权

US06946932B2 Surface acoustic wave resonator with an interdigital transducer divided into regions having a different fixed pitch 有权
标题翻译：具有叉指换能器的表面声波谐振器被分成具有不同固定间距的区域
公开(公告)号：US06946932B2
公开(公告)日：2005-09-20
申请号：US10679480
申请日：2003-10-07
申请人： Michiaki Takagi , Yoshio Maeda , Takashi Yamazaki , Keigo Iizawa
发明人： Michiaki Takagi , Yoshio Maeda , Takashi Yamazaki , Keigo Iizawa
IPC分类号： H01L41/09 , H01L41/18 , H03H9/02 , H03H9/145 , H03H9/25 , H03H9/64
CPC分类号： H03H9/25 , H03H9/02551 , H03H9/14582
摘要： In a substrate in which a reflection coefficient γ of a surface acoustic wave per electrode is small, the invention obtains a Q value or a CI value level, which is equivalent to or higher than that of a related art product, at a device size which is equivalent to the related art product which addresses the problem that the size of a surface acoustic wave resonator becomes larger. A surface acoustic wave resonator includes one interdigital transducer to excite a surface acoustic wave in a propagation direction x on a piezoelectric plate and a pair of reflectors arranged on both sides thereof in the propagation direction. The interdigital transducer is divided into three regions. The electrode fingers of the interdigital transducer of each region are formed at a fixed pitch which differs within 2%. The surface acoustic wave resonator possesses a single peak response. The form in which a vibration displacement envelope amplitude in the interdigital transducer region is normalized is a form which takes a maximum value 1 at the center position, which smoothly takes a value in a range of 0.33 to 0.53 at a position ¼ from both ends, and which smoothly takes a value in a range of 0.048 to 0.177 at positions at both ends.
摘要翻译：在每个电极的表面声波的反射系数γ小的基板中，本发明以如下装置尺寸获得与现有技术产品相同或更高的Q值或CI值电平相当于解决声表面波谐振器的尺寸变大的问题的现有技术的产品。表面声波谐振器包括一个叉指式换能器，以在压电板上的传播方向x上激发表面声波，并且在传播方向的两侧布置一对反射器。叉指换能器分为三个区域。每个区域的叉指换能器的电极指以固定的间距形成，其在2％内不同。表面声波谐振器具有单峰响应。叉指换能器区域中的振动位移包络振幅被归一化的形式是在中心位置处取最大值1的形式，在两端的位置¼平滑地取0.33〜0.53的范围内的值，并且在两端的位置平滑地获得0.048〜0.177的范围的值。

14. 发明授权

US06919622B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06919622B2
公开(公告)日：2005-07-19
申请号：US10774405
申请日：2004-02-10
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
IPC分类号： H01L21/52 , H01L23/31 , H01L23/495 , H01L23/50 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/105 , H01L29/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85205 , H01L2224/8592 , H01L2224/92147 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , H01L2924/00012 , H01L2924/00 , H01L2924/01026 , H01L2924/3512 , H01L2924/0695 , H01L2224/85399
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
摘要翻译：由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小杂散容量，提高信号传输速率和减少电气噪声。

15. 发明授权

US06856218B2 Surface acoustic wave device and communications apparatus using the same 有权
标题翻译：声表面波装置及使用其的通信装置
公开(公告)号：US06856218B2
公开(公告)日：2005-02-15
申请号：US10329445
申请日：2002-12-27
申请人： Takashi Yamazaki , Keigo Iizawa , Shigeo Kanna
发明人： Takashi Yamazaki , Keigo Iizawa , Shigeo Kanna
IPC分类号： H03H9/02 , H03H9/25 , H03H9/64
CPC分类号： H03H9/25 , H03H9/02543
摘要： The invention provides an in-plane rotational ST-cut SAW resonator that is formed of an in-plane rotational ST-cut crystal plate having Eulerian angles of (0°, 113° to 135°, and ±(40° to 49°)). The in-plane rotational ST-cut SAW resonator can include an interdigital transducer (IDT) electrode for exciting a Rayleigh wave on the main surface. The ratio Lt/Pt of the electrode width Lt and the interelectrode pitch Pt of the IDT electrode is 0.5 or more and 0.65 or less. Accordingly, a reduction in the fluctuation in resonance frequency relative to the variations in an IDT electrode of a surface acoustic wave device by using the in-plane rotated ST-cut crystal plate around the Z′-axis can be achieved.
摘要翻译：本发明提供一种面内旋转ST切割SAW谐振器，其由具有（0°，113°至135°和±（40°至49°））的欧拉角的平面内旋转ST切割晶体板形成，）。平面内旋转ST切割SAW谐振器可以包括用于激励主表面上的瑞利波的叉指式换能器（IDT）电极。电极宽度Lt的比率Lt / Pt和IDT电极的电极间间距Pt为0.5以上且0.65以下。因此，通过使用围绕Z'轴的平面内旋转的ST切割晶体板，可以实现相对于声表面波器件的IDT电极的变化的共振频率的波动的减小。

16. 发明授权

US06673282B2 Method for protecting dies in an injection molding machine 有权
标题翻译：在注塑机中保护模具的方法
公开(公告)号：US06673282B2
公开(公告)日：2004-01-06
申请号：US10108987
申请日：2002-03-29
申请人： Haruyuki Matsubayashi , Takamitsu Yamashita , Takashi Yamazaki , Motoyuki Miyauchi , Yutaka Yamaguchi , Masamitsu Suzuki , Makoto Nishizawa
发明人： Haruyuki Matsubayashi , Takamitsu Yamashita , Takashi Yamazaki , Motoyuki Miyauchi , Yutaka Yamaguchi , Masamitsu Suzuki , Makoto Nishizawa
IPC分类号： B29C4576
CPC分类号： B22D17/32 , B29C45/33 , B29C45/661 , B29C45/84
摘要： A stationary die is held on the front surface of a stationary platen and a movable die is held on the front surface of a movable platen. A plurality of monitoring sections are set in advance within a moving range of the movable platen and an upper limit of forward thrust of the movable platen is set for each of the monitoring sections. When the forward thrust of the movable platen reaches the upper limit set in one of the monitoring sections during a die closing operation, it is determined that abnormality occurs to stop the movable platen from moving forward. If a die closing mechanism is of a toggle link type, the forward thrust of the movable platen is calculated based on the thrust of a crosshead which drives a toggle link mechanism, the moving speed of the crosshead, and the moving speed of the movable platen.
摘要翻译：固定模具固定在固定压板的前表面上，并且可移动模具被保持在可动压板的前表面上。在可动压板的移动范围内预先设置多个监视部，并且为每个监视部设定可动压板的向前推力的上限。当在压模闭合操作期间可动压板的向前推力达到设置在其中一个监控部分中的上限时，确定异常发生以使可动压板停止向前移动。如果模具闭合机构是肘节式，则基于驱动肘节连杆机构的十字头的推力，十字头的移动速度和可移动压盘的移动速度来计算可动压板的向前推力。

17. 发明授权

US06617678B2 Semiconductor device 失效
公开(公告)号：US06617678B2
公开(公告)日：2003-09-09
申请号：US10145722
申请日：2002-05-16
申请人： Takashi Yamazaki , Mitsuyoshi Endo , Chiaki Takubo , Katsuhiko Oyama , Takashi Imoto , Mikio Matsui
发明人： Takashi Yamazaki , Mitsuyoshi Endo , Chiaki Takubo , Katsuhiko Oyama , Takashi Imoto , Mikio Matsui
IPC分类号： H01L2302
CPC分类号： H01L25/0657 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/0652 , H01L2225/06524 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2225/06586 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/15153 , H01L2924/1517 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.

18. 发明授权

US06335884B1 Semiconductor memory device and defect remedying method thereof 有权
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US06335884B1
公开(公告)日：2002-01-01
申请号：US09714268
申请日：2000-11-17
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C1300
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
摘要翻译：这里公开了一种半导体存储器件，其中外围电路布置在由纵向中心部分和横向中心部分组成的半导体芯片的交叉区域中，并且其中存储器阵列布置在由交叉区域。由于外围电路布置在芯片的中心部分的这种结构，最长的信号传输路径可以缩短到芯片尺寸的大约一半，以加快DRAM的大容量。

19. 发明授权

US06326681B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06326681B1
公开(公告)日：2001-12-04
申请号：US09482648
申请日：2000-01-13
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
IPC分类号： H01L23495
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/105 , H01L29/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85205 , H01L2224/8592 , H01L2224/92147 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , H01L2924/00012 , H01L2924/00 , H01L2924/01026 , H01L2924/3512 , H01L2924/0695 , H01L2224/85399
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
摘要翻译：由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小杂散容量，提高信号传输速率和减少电气噪声。

20. 发明授权

US6130114A Semiconductor device 失效
公开(公告)号：US6130114A
公开(公告)日：2000-10-10
申请号：US290582
申请日：1999-04-13
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjoh , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjoh , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
IPC分类号： H01L21/52 , H01L23/31 , H01L23/495 , H01L23/50 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/32 , H01L24/49 , H01L25/105 , H01L29/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85205 , H01L2224/8592 , H01L2224/92147 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1088 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

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