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11. 发明授权

US07453313B2 Charge pumping circuit 有权
标题翻译：充电泵电路
公开(公告)号：US07453313B2
公开(公告)日：2008-11-18
申请号：US11637687
申请日：2006-12-13
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： G06F3/02
CPC分类号： H02M3/07 , H03L7/0895 , H03L7/0896
摘要： A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.
摘要翻译：电荷泵浦电路包括：第一开关，用于根据第一控制信号控制推挽操作中的一个; 由与所述第一开关具有不同极性的晶体管构成的电流镜电路; 第二开关，用于根据第二控制信号控制到电流镜电路的电流输入，第二开关由具有与用于构造第一开关的晶体管相同的特性的晶体管构成; 第一MOS电容器，其一端连接到电流镜电路的输入侧; 在其一端接收与推挽操作有关的电流的第二MOS电容器; 以及连接到第一和第二MOS电容器的电压缓冲器。推挽操作中的另一个用电流镜电路的输出电流进行。

12. 发明申请

US20060176091A1 Delay locked loop circuit 审中-公开
标题翻译：延时锁定回路电路
公开(公告)号：US20060176091A1
公开(公告)日：2006-08-10
申请号：US11289753
申请日：2005-11-30
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0891 , H03L7/0895
摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
摘要翻译：延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉）（或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

13. 发明授权

US06246627B1 Semiconductor device capable of cutting off a leakage current in a defective array section and method thereof 有权
标题翻译：能够切断缺陷阵列部分的漏电流的半导体装置及其方法
公开(公告)号：US06246627B1
公开(公告)日：2001-06-12
申请号：US09397239
申请日：1999-09-16
申请人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
发明人： Hiroyuki Yamauchi , Hironori Akamatsu , Toru Iwata , Keiichi Kusumoto , Satoshi Takahashi , Yutaka Terada , Takashi Hirata
IPC分类号： G11C514
CPC分类号： G01R31/3004 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.
摘要翻译：本发明的半导体器件包括：包括多个电路块的阵列部分; 泄漏电流切断部，切断在所述阵列部中的所述多个电路块中的至少一个电路中发生的漏电流; 以及控制部分，用于根据泄漏电流切断信息控制漏电流切断部分。

14. 发明授权

US6145065A Memory access buffer and reordering apparatus using priorities 失效
标题翻译：使用优先级的存储器访问缓冲器和重新排序装置
公开(公告)号：US6145065A
公开(公告)日：2000-11-07
申请号：US67899
申请日：1998-04-29
申请人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
发明人： Satoshi Takahashi , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Yutaka Terada , Takashi Hirata
IPC分类号： G06F13/16 , G06F12/02
CPC分类号： G06F13/1631
摘要： A current problem is that when a DRAM is to be accessed through a data bus, the DRAM is accessed independently of a bank, a row address, etc., and therefore, is inefficient. To solve this problem, an address bus and a data bus are connected to a main memory part independently of each other, a temporary memory part for holding a plurality of addresses in advance is disposed on the address bus side and holds addresses for every access to the main memory part regardless of transfer of data, thereby pipelining address inputting cycles. Further, for the purpose of an effective operation of the main memory part, using the addresses which are held, the addresses are rearranged in such a manner that addresses with the same row addresses become continuous to each other, or when there are not addresses with the same row addresses, addresses different banks from each other become continuous to each other, and the memory is thereafter accessed. This reduces the number of precharges, shortens a standby period which is necessary for a precharge, and realizes accessing while reducing a wasteful use of time.
摘要翻译：目前的问题在于，当通过数据总线访问DRAM时，独立于存储体，行地址等访问DRAM，因此是低效的。为了解决这个问题，地址总线和数据总线彼此独立地连接到主存储器部分，预先存储多个地址的临时存储器部分设置在地址总线侧，并且保存地址以进行每次访问主存储部分不管数据传输，从而流水线地址输入周期。此外，为了主存储器部分的有效操作，使用所保存的地址，地址被重新排列，使得具有相同行地址的地址彼此连续，或者当没有地址与相同的行地址，彼此不同的存储体彼此变得连续，并且此后访问存储器。这减少了预充电次数，缩短了预充电所需的待机时间，并实现了访问，同时减少了浪费时间的使用。

15. 发明授权

US08040168B2 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US08040168B2
公开(公告)日：2011-10-18
申请号：US11188855
申请日：2005-07-26
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： H03L7/06 , G05F3/02
CPC分类号： H02M3/07
摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.
摘要翻译：电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。

16. 发明申请

US20080303567A1 DELAY LOCKED LOOP CIRCUIT 有权
标题翻译：延迟锁定环路
公开(公告)号：US20080303567A1
公开(公告)日：2008-12-11
申请号：US12033707
申请日：2008-02-19
申请人： Shiro SAKIYAMA , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
发明人： Shiro SAKIYAMA , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata , Hideki Yoshii , Yasuyuki Doi , Makoto Hattori
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/07 , H03L7/0891 , H03L7/0895
摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
摘要翻译：延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉）（或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

17. 发明申请

US20060097772A1 Charge pump circuit 有权
标题翻译：电荷泵电路
公开(公告)号：US20060097772A1
公开(公告)日：2006-05-11
申请号：US11188855
申请日：2005-07-26
申请人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
发明人： Shiro Sakiyama , Yusuke Tokunaga , Shiro Dosho , Toru Iwata , Takashi Hirata
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.
摘要翻译：电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。

18. 发明授权

US6140864A Circuit for controlling leakage current in large scale integrated circuits 失效
标题翻译：用于控制大规模集成电路中的漏电流的电路
公开(公告)号：US6140864A
公开(公告)日：2000-10-31
申请号：US927061
申请日：1997-09-10
申请人： Takashi Hirata , Toru Iwata , Hironori Akamatsu
发明人： Takashi Hirata , Toru Iwata , Hironori Akamatsu
IPC分类号： G06F1/26 , G05F3/02
CPC分类号： G06F1/26
摘要： In an LSI circuit, respective voltages on power-source lines connected to the respective sources of transistors which are turned OFF in a circuit block in the standby state are controlled by a power-source-voltage control circuit to vary in response to variations in the threshold voltages of the transistors. Consequently, the differential voltage (Vgs-Vt) between the gate-to-source voltage Vgs of each of the transistors and the threshold voltage Vt thereof is held constant at a given value, so that an OFF-state leakage current flowing through the transistor in the circuit block in the standby state is reduced and held constant at a given value. What results is a reduction in the power consumption of the circuit block in the standby state.
摘要翻译：在LSI电路中，通过电源电压控制电路来控制在待机状态下在电路块中断开的与晶体管的各个源连接的电源线上的各个电压，以响应于晶体管的阈值电压。因此，每个晶体管的栅 - 源电压Vgs与其阈值电压Vt之间的差分电压（Vgs-Vt）保持恒定在给定值，使得流过晶体管的截止状态漏电流处于待机状态的电路块减小并保持恒定在给定值。在待机状态下电路块的功耗降低是什么结果。

19. 发明授权

US6137306A Input buffer having adjustment function for suppressing skew 有权
标题翻译：具有用于抑制偏斜的调节功能的输入缓冲器
公开(公告)号：US6137306A
公开(公告)日：2000-10-24
申请号：US345012
申请日：1999-07-02
申请人： Takashi Hirata , Toru Iwata
发明人： Takashi Hirata , Toru Iwata
IPC分类号： H03K19/0175 , H03K5/00 , H03K5/08 , H03K5/13 , H03K19/003 , H04L25/14 , H03K17/16
CPC分类号： H04L25/14 , H03K19/00323 , H03K5/08 , H03K5/13 , H03K2005/00058 , H03K2005/00156
摘要： An input buffer of the present invention includes: a plurality of receiver circuits for performing different phase adjustments on an input signal, and outputting the differently phase-adjusted signals; a pattern detection circuit for detecting a period of time for which a voltage of the input signal has remained unchanged; and a signal selection circuit for selecting one of the output signals received from the receiver circuits based on the detection result from the pattern detection circuit.
摘要翻译：本发明的输入缓冲器包括：多个接收器电路，用于对输入信号执行不同的相位调整，并输出不同的相位调整信号; 用于检测输入信号的电压保持不变的时间段的模式检测电路; 以及信号选择电路，用于基于来自图案检测电路的检测结果来选择从接收器电路接收的输出信号之一。

20. 发明授权

US6009024A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US6009024A
公开(公告)日：1999-12-28
申请号：US46880
申请日：1998-03-24
申请人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
发明人： Takashi Hirata , Hiroyuki Yamauchi , Hironori Akamatsu , Keiichi Kusumoto , Toru Iwata , Satoshi Takahashi , Yutaka Terada
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/06
摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.
摘要翻译：本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管，并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。

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