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11. 发明授权

US06631486B1 Semiconductor integrated circuit and method for testing the same 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US06631486B1
公开(公告)日：2003-10-07
申请号：US09405015
申请日：1999-09-27
申请人： Yoshihide Komatsu , Tadahiro Yoshida , Yukio Arima
发明人： Yoshihide Komatsu , Tadahiro Yoshida , Yukio Arima
IPC分类号： G01R3128
CPC分类号： G01R31/31905 , G01R31/31926
摘要： A test enable signal Data_En is output from a data generator 11 in a tester 10 to a device under a test (DUT) 20. In the DUT 20, a first logic circuit 21 converts a signal pattern with an ordinary transfer rate, which has been stored on a register 28, into a high-transfer-rate signal pattern SpeedData_Tx with a high rate. And a transmitter 22 transmits the high-transfer-rate signal. During a test, the high-transfer-rate signal transmitted is received by, a receiver 23 with a switch 24 turned ON. Then, the high-transfer-rate signal received is output to a second logic circuit 26, which converts the high-transfer-rate signal into a low-transfer-rate signal Data_Rx with an ordinary rate. Finally, the low-transfer-rate signal is output to the tester 10 and compared to an expected value thereof by a comparator 12. In this manner, a semiconductor device operating at a high speed can be tested using a tester operating at a lower speed.
摘要翻译：测试使能信号Data_En从测试器10中的数据发生器11输出到被测设备（DUT）20。在DUT 20中，第一逻辑电路21以一般传输速率转换信号模式存储在寄存器28中，以高速率转换成高传输速率信号模式SpeedData_Tx。并且发射机22发送高传输速率信号。在测试期间，传输的高传输速率信号由开关24接通的接收机23接收。然后，所接收的高传输速率信号被输出到第二逻辑电路26，第二逻辑电路26将高传输速率信号以普通速率转换成低传输速率信号Data_Rx。最后，将低传输速率信号输出到测试器10，并通过比较器12与其期望值进行比较。以这种方式，可以使用以较低速度操作的测试仪来测试以高速工作的半导体器件。

12. 发明授权

US06498519B1 Voltage control circuit network device and method of detecting voltage 有权
标题翻译：电压控制电路网络装置及电压检测方法
公开(公告)号：US06498519B1
公开(公告)日：2002-12-24
申请号：US09498339
申请日：2000-02-04
申请人： Yutaka Terada , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Satoshi Takahashi , Takashi Hirata , Yukio Arima , Yoshihide Komatsu
发明人： Yutaka Terada , Hiroyuki Yamauchi , Hironori Akamatsu , Tadahiro Yoshida , Satoshi Takahashi , Takashi Hirata , Yukio Arima , Yoshihide Komatsu
IPC分类号： H03K5153
CPC分类号： G01R19/16547
摘要： A voltage control circuit for implementing, e.g., the CPS function in which a high-accuracy comparison is performed between a high external voltage and a reference voltage. A diode-connected transistor converts the external voltage to a voltage lower than the external voltage in conjunction with an external voltage dropping resistor. A comparator compares the converted voltage with a specified comparison voltage. The size of the transistor is determined such that the ratio of an increment of the converted voltage to an increment of the external voltage is sufficiently high in a comparison region in which the external voltage is close to the reference voltage. A clamping circuit clamps the converted voltage with a specified limit voltage such that the converted voltage does not exceed the withstand voltage of the circuit.
摘要翻译：一种用于实现例如在高外部电压和参考电压之间进行高精度比较的CPS功能的电压控制电路。二极管连接的晶体管将外部电压转换为低于外部电压的电压，并结合外部降压电阻。比较器将转换的电压与指定的比较电压进行比较。确定晶体管的尺寸，使得在外部电压接近参考电压的比较区域中，转换电压的增量与外部电压的增量的比率足够高。钳位电路以转换后的电压将指定的极限电压钳位，使转换后的电压不超过电路的耐压。

13. 发明授权

US4816853A Camera system with plural interchangeable accessories sharing a common serial data bus 失效
标题翻译：具有多个可互换配件的相机系统共享一个通用的串行数据总线
公开(公告)号：US4816853A
公开(公告)日：1989-03-28
申请号：US820656
申请日：1986-01-21
申请人： Yoshiiku Kikukawa , Masayuki Nakasa , Tadahiro Yoshida , Mashio Kitaura , Masaaki Nakai , Takanobu Omaki , Nobuyuki Taniguchi
发明人： Yoshiiku Kikukawa , Masayuki Nakasa , Tadahiro Yoshida , Mashio Kitaura , Masaaki Nakai , Takanobu Omaki , Nobuyuki Taniguchi
IPC分类号： G03B7/091 , G03B7/16 , G03B7/00 , G03B15/05
CPC分类号： G03B7/091 , G03B7/16
摘要： A camera system including a camera body and a camera accessory attachable to the camera body, such as an interchangeable back lid, an interchangeable lens, a flash device and so on, is disclosed. In the system, a plurality of circuits provided in the plurality of camera accessories are controlled by a microcomputer provided in the camera body. Data is transmitted between the microcomputer and the circuits using a serial data bus and synchronizing clock line connected therebetween. The circuit to receive the data sent from the microcomputer, or the circuit which should send the data to the microcomputer are selected by the microcomputer through chip select lines provided between the microcomputer and each circuit.
摘要翻译：公开了一种照相机系统，其包括相机主体和附接到照相机主体的相机附件，诸如可互换后盖，可互换镜头，闪光灯装置等。在该系统中，设置在多个照相机附件中的多个电路由设置在相机机体中的微型计算机控制。使用串行数据总线在微机和电路之间传输数据，同时连接其间的同步时钟线。由微型计算机通过微型计算机和各电路之间提供的芯片选择线选择接收从微型计算机发送的数据的电路，或将数据发送到微机的电路。

14. 发明授权

US4623151A Seal means for a stirling engine or the like 失效
标题翻译：斯特林发动机等的密封装置
公开(公告)号：US4623151A
公开(公告)日：1986-11-18
申请号：US721702
申请日：1985-04-10
申请人： Kazuo Kashiwamura , Tadahiro Yoshida , Toshihide Koda , Michio Fujiwara
发明人： Kazuo Kashiwamura , Tadahiro Yoshida , Toshihide Koda , Michio Fujiwara
IPC分类号： F02G1/05 , F02G1/053 , F16J15/16 , F16J15/40
CPC分类号： F02G1/0535 , F02G2243/00 , F02G2243/08 , F02G2253/00 , F02G2253/03 , F02G2253/08 , F02G2270/50 , F02G2270/85 , F02G2275/40 , Y10S277/902
摘要： A seal means for use in the Stirling engine or the like, the seal means comprising: a cylinder including a piston reciprocating therein, and a buffer chamber located in one of the spaces produced at the both sides of the piston; a tank for storing the working fluid in the buffer chamber when the engine is at rest, the tank being located outside the cylinder; a means for introducing the working fluid in the tank into the buffer chamber under pressure when the engine is started; a crank shaft driven by means of the piston through a piston rod; a crankcase for accommodating the crank shaft; a plurality of packings for preventing the working fluid in the buffer chamber from entering the crankcase by flowing along the outer surface of the moving piston rod, the packings being arranged in contact with the outer surface of the piston rod; and a means for returning the working fluid leaked in the packings from the buffer chamber through the moving piston rod to the buffer chamber.
摘要翻译：一种在斯特林发动机等中使用的密封装置，所述密封装置包括：气缸，其包括在其中往复运动的活塞;以及缓冲室，位于活塞两侧产生的空间之一; 用于在发动机处于静止状态时将工作流体存储在缓冲室中的罐，所述罐位于所述气缸外部; 当发动机起动时，将压力下的工作流体引入缓冲室中的装置; 通过活塞通过活塞杆驱动的曲柄轴; 用于容纳曲柄轴的曲轴箱; 用于防止缓冲室中的工作流体沿着活动活塞杆的外表面流动而进入曲轴箱的多个填料，所述密封件布置成与活塞杆的外表面接触; 以及用于将填充物中泄漏的工作流体从缓冲室通过移动活塞杆返回到缓冲室的装置。

15. 发明授权

US4598412A Binary digital data signal reproducing circuit in digital data transmission system 失效
标题翻译：数字数据传输系统中的二进制数字数据信号再现电路
公开(公告)号：US4598412A
公开(公告)日：1986-07-01
申请号：US700082
申请日：1985-02-11
申请人： Tadahiro Yoshida
发明人： Tadahiro Yoshida
IPC分类号： H04L25/03 , H04L25/24 , H04L25/08
CPC分类号： H04L25/242
摘要： A reproducer for reproducing a binary digital data signal from a signal received at a receiver side. A pulse train is detected from the received signal at a pulse detector. Each pulse in the pulse train sets a first D-type flip-flop, which is, in turn, cleared by a clear pulse produced by a second D-type flip-flop in response to a clock pulse just after the first D-type flip-flop is set. The output of the first D-type flip-flop is applied to a data input terminal of a third D-type flip-flop and is taken into the third D-type flip-flop by the same clock pulse. The clock pulse repetition frequency is synchronous with the binary digital data signal. Thus, the reproduced binary digital data signal is obtained on an output of the third D-type flip-flop.
摘要翻译：一种用于从在接收机侧接收的信号再现二进制数字数据信号的再现器。在脉冲检测器处从接收到的信号检测脉冲串。脉冲串中的每个脉冲设置第一D型触发器，该第一D型触发器又由第二D型触发器产生的清除脉冲清除，以响应刚刚在第一D型触发器之后的时钟脉冲触发器设置。第一D型触发器的输出被施加到第三D型触发器的数据输入端，并被相同的时钟脉冲带入第三D型触发器。时钟脉冲重复频率与二进制数字数据信号同步。因此，在第三D型触发器的输出上获得再现的二进制数字数据信号。

16. 发明授权

US4573173A Clock synchronization device in data transmission system 失效
标题翻译：数据传输系统中的时钟同步装置
公开(公告)号：US4573173A
公开(公告)日：1986-02-25
申请号：US618410
申请日：1984-06-06
申请人： Tadahiro Yoshida
发明人： Tadahiro Yoshida
IPC分类号： H04L7/02 , H04L7/033 , H04L7/00
CPC分类号： H04L7/0338
摘要： A circuit for obtaining a clock pulse synchronized to a data signal received at a receiving side, which has a plurality of clock pulses having a repetition frequency equal to that of a clock in a transmission side but being different from one another in phase. On reception of the first data bit of the received data signal, the timing of the first data bit is detected at a detection circuit in reference to the plurality of clock pulses. According to the detected timing, a selector circuit selects one of the plurality of clock pulses with a predetermined constant phase difference from the received data signal.The detection circuit comprises D-type flip-flops, and the selector circuit comprises AND gates.
摘要翻译：一种用于获得与在接收侧接收的数据信号同步的时钟脉冲的电路，其具有多个时钟脉冲，所述时钟脉冲的重复频率等于发送侧的时钟的重复频率，但是彼此相位不同。在接收到接收到的数据信号的第一数据位时，参考多个时钟脉冲在检测电路处检测第一数据位的定时。根据检测到的定时，选择器电路从接收的数据信号中选择具有预定的恒定相位差的多个时钟脉冲之一。检测电路包括D型触发器，选择电路包括与门。

17. 发明授权

US06768334B1 Signal transmitting receiving apparatus 有权
标题翻译：信号发送接收装置
公开(公告)号：US06768334B1
公开(公告)日：2004-07-27
申请号：US09553308
申请日：2000-04-20
申请人： Hiroyuki Yamauchi , Tadahiro Yoshida
发明人： Hiroyuki Yamauchi , Tadahiro Yoshida
IPC分类号： H03K19003
CPC分类号： H01P5/02
摘要： A signal transmitting/receiving apparatus according to the present invention includes: a transmitting device for transmitting data; a receiving device for receiving the data; a data line for transmitting the data; and a supply line for transmitting a bias voltage for determining a voltage of the data line, wherein the transmitting device and the receiving device are connected to each other through the data line and the supply line, the transmitting device including: a driver circuit for outputting the data to the data lines and a bias generating means for generating the bias voltage and outputting the bias voltage to the supply line, the receiving device including: a terminating resistor connected to the data line; and a receiver circuit for detecting the data from the data line, wherein the data line is connected to the supply line via the terminating resistor.
摘要翻译：根据本发明的信号发送/接收装置包括：发送装置，用于发送数据; 用于接收数据的接收装置; 用于发送数据的数据线; 以及用于发送用于确定数据线的电压的偏置电压的电源线，其中所述发送装置和所述接收装置通过所述数据线和所述供给线彼此连接，所述发送装置包括：驱动器电路，用于输出数据线路的数据和偏置产生装置，用于产生偏置电压并将偏置电压输出到电源线，所述接收装置包括：连接到数据线的终端电阻; 以及用于检测来自数据线的数据的接收器电路，其中数据线经由终端电阻器连接到电源线。

18. 发明授权

US06356144B1 LSI core including voltage generation circuit and system LSI including the LSI core 有权
标题翻译： LSI核心，包括具有LSI核心的电压产生电路和系统LSI
公开(公告)号：US06356144B1
公开(公告)日：2002-03-12
申请号：US09580139
申请日：2000-05-30
申请人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Tadahiro Yoshida , Yoshihide Komatsu
发明人： Hironori Akamatsu , Yutaka Terada , Takashi Hirata , Tadahiro Yoshida , Yoshihide Komatsu
IPC分类号： H01L2500
CPC分类号： G06F13/4086 , H01L2224/05554
摘要： An LSI core includes a first terminal; a second terminal; and a voltage generation circuit for generating a voltage. The first terminal is connected to a first external line provided outside the LSI core. The second terminal is connected to the first external line and to a second external line provided outside the LSI core. The voltage generation circuit includes a voltage generation section for generating the voltage, an output section for outputting the voltage generated by the voltage generation section to the first external line through the first terminal, and an input section for receiving the voltage, output to the first external line by the output section, through the second external line and the second terminal.
摘要翻译： LSI核心包括第一终端; 第二个终端以及用于产生电压的电压产生电路。第一端子连接到设置在LSI核心外部的第一外部线路。第二端子连接到第一外部线路和连接到设置在LSI核心外部的第二外部线路。电压产生电路包括用于产生电压的电压产生部分，用于通过第一端子将由电压产生部分产生的电压输出到第一外部线路的输出部分和用于接收电压的输入部分，输出到第一外部线由输出部分，通过第二个外部线路和第二个终端。

19. 发明授权

US5515101A Title generator for a video camera 失效
标题翻译：摄像机的标题发生器
公开(公告)号：US5515101A
公开(公告)日：1996-05-07
申请号：US217454
申请日：1994-03-24
申请人： Tadahiro Yoshida
发明人： Tadahiro Yoshida
IPC分类号： H04N5/272 , H04N5/225
CPC分类号： H04N5/272
摘要： A title generator (titler) for a video camera judges whether a title fits the current time (month, season, etc.) and selects only those titles adequate to the time, thereby preventing unnecessary titles from appearing on the display and saving title selecting time. Also disclosed is a video camera system with a titler including an external memory which stores a group or groups of relevant titles. The external title memory can be used in combination with a conventional internal title memory.
摘要翻译：用于摄像机的标题生成器（滴定器）判断标题是否符合当前时间（月，季节等），并且仅选择足够时间的标题，从而防止不必要的标题出现在显示器上并保存标题选择时间。还公开了一种具有滴定器的摄像机系统，其包括存储一组或多组相关标题的外部存储器。外部标题存储器可以与传统的内部标题存储器组合使用。

20. 发明授权

US5333030A Camera system 失效
标题翻译：相机系统
公开(公告)号：US5333030A
公开(公告)日：1994-07-26
申请号：US972739
申请日：1992-11-06
申请人： Yoshiiku Kikukawa , Masayuki Nakasa , Tadahiro Yoshida , Mashio Kitaura , Masaaki Nakai , Takanobu Omaki , Nobuyuki Taniguchi
发明人： Yoshiiku Kikukawa , Masayuki Nakasa , Tadahiro Yoshida , Mashio Kitaura , Masaaki Nakai , Takanobu Omaki , Nobuyuki Taniguchi
IPC分类号： G03B7/091 , G03B7/16 , G03B17/00
CPC分类号： G03B7/16 , G03B7/097
摘要： A camera system including a camera body and a camera accessory attachable to the camera body, such as an interchangeable back lid, an interchangeable lens, a flash device and so on, is disclosed. In the system, a plurality of circuits provided in plurality of camera accessories are controlled by a microcomputer provided in the camera body. Data is transmitted between the microcomputer and the circuits using a serial data bus and synchronizing clock line connected therebetween. The circuit to receive the data sent from the microcomputer, or the circuit which should send the data to the microcomputer are selected by the microcomputer through chip select lines provided between the microcomputer and each circuit.
摘要翻译：公开了一种照相机系统，其包括相机主体和附接到照相机主体的相机附件，诸如可互换后盖，可互换镜头，闪光灯装置等。在该系统中，设置在多个相机附件中的多个电路由设置在相机机体中的微型计算机控制。使用串行数据总线在微机和电路之间传输数据，同时连接其间的同步时钟线。由微型计算机通过微型计算机和各电路之间提供的芯片选择线选择接收从微型计算机发送的数据的电路，或将数据发送到微机的电路。

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