会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 12. 发明授权
    • Recording classification of instructions executed by a computer
    • 记录计算机执行指令的分类
    • US06954923B1
    • 2005-10-11
    • US09348317
    • 1999-07-07
    • John S. Yates, Jr.David L. ReeseKorbin S. Van Dyke
    • John S. Yates, Jr.David L. ReeseKorbin S. Van Dyke
    • G06F9/318G06F9/38G06F9/42G06F9/44
    • G06F9/3851G06F9/30174G06F9/30189G06F9/3802G06F9/3861G06F9/4486
    • An instruction processor to execute two instruction sets. Instructions are stored in different virtual memory pages of a single address space, and are coded for computers of two different instruction sets, and use of two different calling conventions. The instruction processor interprets instructions under, alternately, the first or second instruction set as directed by a first flag stored in table entries corresponding to memory pages for the instructions. The processor recognizes when program execution has transferred from a page of instructions using the first data storage convention to a page of instructions using the second data storage convention, as indicated by a second flag stored in the table entries, and then adjusts a data storage content of the computer from the first storage convention to the second data storage convention. A history record provides a record of a classification of a recently-executed instruction.
    • 一个执行两个指令集的指令处理器。 指令存储在单个地址空间的不同虚拟存储器页面中,并且被编码用于两个不同指令集的计算机,并且使用两种不同的调用约定。 指令处理器根据存储在对应于指令的存储器页的表条目中的第一标志的指示,来解释第一或第二指令集下的指令。 处理器识别何时使用第二数据存储约定将使用第一数据存储约定的指令页面的程序执行转移到指令页,如由表条目中存储的第二标志所指示的,然后调整数据存储内容 的计算机从第一存储惯例到第二数据存储惯例。 历史记录提供了最近执行的指令的分类记录。
    • 16. 发明授权
    • Logarithmic conversion apparatus
    • 对数转换装置
    • US4626825A
    • 1986-12-02
    • US751305
    • 1985-07-02
    • Wayne P. BurlesonLawrence F. WagnerKorbin S. Van Dyke
    • Wayne P. BurlesonLawrence F. WagnerKorbin S. Van Dyke
    • G06F1/03H03M7/24H03M7/50
    • H03M7/24G06F1/0307G06F7/4833
    • A logarithmic converting apparatus for converting a digital binary integer into logarithmic representation and for converting logarithmic representation into digital binary integer is disclosed. The apparatus determines the bit position of a leading non-zero bit of an integer, shifts the integer such that the leading non-zero bit is the leftmost bit. A look-up table receives the shifted integer and provides a number representative of the mantissa portion of the logarithm of the shifted number. An encoder receives a Point Set Input value, a scale value for said integer, and the number of binary positions shifted and generates the exponential portion of the logarithm of the integer. For converting logarithmic representation of a number into integer representation, the apparatus has a look-up table which receives the mantissa component of the logarithmic representation and provides a first number. A decoder receives the exponential component of the logarithmic representation and a Point Set Output value, a scale value for said integer, and supplies a shifted signal. The shifted signal is supplied to a shifter along with the first number and the shifter shifts the first number by the shift signal to produce the integer.
    • 公开了一种用于将数字二进制整数转换成对数表示并将对数表示转换成数字二进制整数的对数转换装置。 该装置确定整数的前导非零位的位位置,使整数移位,使得前导非零位是最左位。 查找表接收移位的整数,并提供代表移位数的对数的尾数部分的数字。 编码器接收点集输入值,所述整数的比例值,并且二进制位置的数量被移位,并且生成整数的对数的指数部分。 为了将数字的对数表示转换为整数表示,装置具有接收对数表示的尾数分量并且提供第一数字的查找表。 解码器接收对数表示的指数分量和点集输出值,所述整数的比例值,并提供移位信号。 移位信号与第一个数字一起提供给移位器,移位器将第一个数字移位移位信号以产生整数。
    • 17. 发明申请
    • Apparatus for executing programs for a first computer architechture on a computer of a second architechture
    • 用于在第二建筑物的计算机上执行用于第一计算机建筑物的程序的装置
    • US20080216073A1
    • 2008-09-04
    • US11904007
    • 2007-09-25
    • John S. YatesMatthew F. StorchSandeep NijhawanDale R. JurichKorbin S. Van Dyke
    • John S. YatesMatthew F. StorchSandeep NijhawanDale R. JurichKorbin S. Van Dyke
    • G06F9/46
    • G06F9/45554G06F9/30174G06F9/30189G06F9/3861
    • Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler. The entry exception, exit exception, entry handler, and exit handler are cooperatively designed to maintain an association between a one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread beyond those resources whose association with the thread is maintained by the operating system.
    • 在第二不同架构的计算机上执行以第一计算机的指令集编码的程序。 操作系统维护一组并发线程中的每一个与线程上下文的一组计算机资源之间的关联。 在不修改计算机的预先存在的操作系统的情况下,将在指定的入口点或指定条件下建立要在操作系统的每个条目上提出的入口异常。 条目异常具有相关联的条目处理程序,其被编程为在将修改的上下文传送到操作系统之前,保存中断的线程的上下文并修改线程上下文。 在操作系统的每次恢复之后建立恢复异常,补充指定条目之一。 恢复异常具有相关联的退出处理程序,其被编程为恢复由相应执行的条目处理程序保存的上下文。 入口异常,退出异常,条目处理程序和退出处理程序被协调地设计为通过由操作系统引发的上下文变化来维护线程中的一个线程和线程的扩展上下文之间的关联,扩展的上下文包括 与线程相关联的计算机超出与该线程的关联的那些资源由操作系统维护。
    • 18. 发明授权
    • Modifying program execution based on profiling
    • 基于分析修改程序执行
    • US06763452B1
    • 2004-07-13
    • US09339797
    • 1999-06-24
    • Paul H. HohenseeJohn S. Yates, Jr.Korbin S. Van DykeDavid L. ReeseStephen C. Purcell
    • Paul H. HohenseeJohn S. Yates, Jr.Korbin S. Van DykeDavid L. ReeseStephen C. Purcell
    • G06F900
    • G06F9/45558G06F9/45541G06F9/45554G06F2009/45583
    • A method and a multiprocessor computer for execution of the method. A first CPU has a general register file, an instruciton pipeline, and profile circuitry. The profile circuitry is operatively interconnected and under common hardware control with the instruction pipeline. The profile circuitry and instruction pipeline are cooperatively interconnected to detect the occurrence of profileable events occurring in the instruction pipeline. The profile circuitry is operable without software intervention to effect recording of profile information describing the profileable events into the general register file, without first capturing the information into a main memory of the computer. The recording is essentially concurrent with the occurrence of the profileable events. A second CPU is configured to analyze the generated profile data, while the execution and profile data generation continue on the first CPU, and to control the execution of the program on the first CPU based at least in part on the analysis of the collected profile data.
    • 一种用于执行该方法的方法和多处理器计算机。 第一个CPU有一个通用寄存器文件,一个通道管道和一个轮廓电路。 配置文件电路与指令管道可操作地互连,并在通用的硬件控制下。 配置文件电路和指令流水线协同互连,以检测在指令流水线中发生的可轮廓事件的发生。 配置文件电路可操作而无需软件干预,以便将描述可描述事件的简档信息记录到通用寄存器文件中,而无需首先将信息捕获到计算机的主存储器中。 录音本质上与可配置事件的发生同时发生。 第二CPU被配置为分析生成的简档数据,同时在第一CPU上继续执行和简档数据生成,并且至少部分地基于所收集的简档数据的分析来控制第一CPU上的程序的执行 。
    • 19. 发明授权
    • Detecting modification to computer memory by a DMA device
    • US06549959B1
    • 2003-04-15
    • US09434198
    • 1999-11-04
    • John S. YatesDavid L. ReeseKorbin S. Van Dyke
    • John S. YatesDavid L. ReeseKorbin S. Van Dyke
    • G06F1328
    • G06F9/45558G06F9/45554G06F2009/45583
    • A method and computer for executing the method. A CPU is programmed to execute first and second processes, the first process programmed to generate a second representation in a computer memory of information of the second process stored in the memory in a first representation. A main memory divided into pages for management by a virtual memory manager that uses a table stored in the memory. DMA (direct memory access) monitoring circuitry and/or software is designed to monitor DMA memory write transactions to a main memory of a computer by a DMA device of the computer; to detect when the first representation is overwritten by a DMA memory write transaction initiated by the second process, without the second process informing the first process of the DMA memory write transaction, the detecting guaranteed to occur no later than the next access of the second representation following the DMA memory write transaction; to record an indication of a location in the main memory written by the DMA memory write transaction, the DMA monitoring circuitry designed to operate without being informed of the DMA memory write transaction by a CPU of the computer before initiation of the DMA memory write transaction, and to provide the indication to the CPU on request; and to report to the first process that the first representation is overwritten by a DMA memory write transaction. The DMA monitoring circuitry includes a plurality of registers outside the address space of the main memory, each register including an address tag and a vector of memory cells, and control circuitry designed to establish an association between a one of the plurality of registers with a region of the memory when a modification to the region is detected by setting the address tag of the one register to an approximation of the address of the region, and to set the values of the memory cells of the vector to record a fine indication of the address of a memory location modified, the control circuitry being operable without continuing supervisory control of a CPU of the computer. Circuitry is designed to record indications of modification to pages of the main memory into the registers. Read circuitry is designed to respond to a read request from the CPU by providing an address of a modified memory location. The virtual memory management tables do not provide backing store for the modification indications stored in the registers.