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11. 发明申请

US20080093651A1 FLASH MEMORY DEVICES AND METHODS FOR FABRICATING FLASH MEMORY DEVICES 失效
标题翻译：闪速存储器件和用于制造闪速存储器件的方法
公开(公告)号：US20080093651A1
公开(公告)日：2008-04-24
申请号：US11700084
申请日：2007-01-31
申请人： Jai-Hyuk Song , Jeong-Hyuk Choi , Ok-Cheon Hong
发明人： Jai-Hyuk Song , Jeong-Hyuk Choi , Ok-Cheon Hong
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/66833 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L29/66825 , H01L29/7881 , H01L29/792
摘要： A flash memory device includes a cell string having a plurality of cell transistors connected in series, and a string selection transistor and a ground selection transistor connected to both ends of the cell string, respectively, wherein the cell transistor has a channel impurity concentration higher than a channel impurity concentration of at least one of the string selection transistor and the ground selection transistor.
摘要翻译：一种闪速存储器件，包括串联有多个单元晶体管的单元串，以及串联选择晶体管和接地选择晶体管，分别连接到单元串的两端，其中单元晶体管的沟道杂质浓度高于串选择晶体管和接地选择晶体管中的至少一个的沟道杂质浓度。

12. 发明申请

US20080093648A1 NON-VOLATILE MEMORY DEVICES INCLUDING DOUBLE DIFFUSED JUNCTION REGIONS AND METHODS OF FABRICATING THE SAME 有权
标题翻译：非易失性存储器件，包括双重扩散接点区域及其制造方法
公开(公告)号：US20080093648A1
公开(公告)日：2008-04-24
申请号：US11675372
申请日：2007-02-15
申请人： Dong Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
发明人： Dong Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.
摘要翻译：非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度与其紧邻的多个存储单元门。还讨论了相关的制造方法。

13. 发明授权

US07283393B2 NAND flash memory device and method of fabricating the same 失效
公开(公告)号：US07283393B2
公开(公告)日：2007-10-16
申请号：US11483466
申请日：2006-07-10
申请人： Jai-Hyuk Song , Jeong-Hyuk Choi
发明人： Jai-Hyuk Song , Jeong-Hyuk Choi
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A NAND type flash memory device includes a semiconductor substrate, word lines, first and second selection lines, tunnel insulation layers, and selection gate insulation layers. The semiconductor substrate includes a memory transistor region and a selection transistor region. The word lines are arranged in the memory transistor region of the semiconductor substrate, and the selection lines are arranged in the selection transistor region of the semiconductor substrate. The tunnel insulation layers are interposed between the word lines and the semiconductor substrate, and the selection gate insulation layers are interposed between the selection lines and the semiconductor substrate and have a thinner thickness than the thickness of the tunnel insulation layers. Also, the selection gate insulation layers have a thinner thickness in their center region than in their edge portions.

14. 发明申请

US20070007580A1 Non-Volatile Memory Devices Having Floating Gates that Define a Void and Methods of Forming Such Devices 审中-公开
标题翻译：具有定义空隙的浮动门的非易失性存储器件以及形成这种器件的方法
公开(公告)号：US20070007580A1
公开(公告)日：2007-01-11
申请号：US11428690
申请日：2006-07-05
申请人： Jai-Hyuk Song , Jeong-Hyuk Choi , Ki-Nam Kim , Jong-Kwang Lim
发明人： Jai-Hyuk Song , Jeong-Hyuk Choi , Ki-Nam Kim , Jong-Kwang Lim
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/40114
摘要： Non-volatile memory devices include a floating gate having a lower portion and a pair of walls extending upward from opposite edges of the lower portion to define a void. An overlap area between adjacent floating gates is decreased by a side area of the void defined by the lower portion and the walls, so that a parasitic electrostatic capacitance can be reduced.
摘要翻译：非易失性存储器件包括具有下部的浮动栅极和从下部的相对边缘向上延伸的一对壁以限定空隙。相邻浮动栅极之间的重叠区域由下部和壁限定的空隙的侧面面积减小，从而可以减小寄生静电电容。

15. 发明授权

US07867849B2 Method of manufacturing a non-volatile semiconductor device 有权
标题翻译：制造非易失性半导体器件的方法
公开(公告)号：US07867849B2
公开(公告)日：2011-01-11
申请号：US12222074
申请日：2008-08-01
申请人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
发明人： Choong-Ho Lee , Jai-Hyuk Song , Dong-Uk Choi , Suk-Kang Sung
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Example embodiments relate to methods of fabricating a non-volatile memory device. According to example embodiments, a method of fabricating a non-volatile memory device may include forming at least one gate structure on an upper face of a substrate. The at least one gate structure may include a tunnel insulation layer pattern, a charge storing layer pattern, a dielectric layer pattern and a control gate. According to example embodiments, a method of fabricating a non-volatile memory device may also include forming a silicon nitride layer on the upper face of the substrate to cover the at least one gate structure, forming an insulating interlayer on the silicon nitride layer on the upper face of the substrate, and providing an annealing gas toward the upper face of the substrate and a lower face of the substrate to cure defects of the tunnel insulation layer pattern.
摘要翻译：示例实施例涉及制造非易失性存储器件的方法。根据示例性实施例，制造非易失性存储器件的方法可以包括在衬底的上表面上形成至少一个栅极结构。至少一个栅极结构可以包括隧道绝缘层图案，电荷存储层图案，电介质层图案和控制栅极。根据示例实施例，制造非易失性存储器件的方法还可以包括在衬底的上表面上形成氮化硅层以覆盖至少一个栅极结构，在氮化硅层上形成绝缘中间层并且朝向基板的上表面和基板的下表面提供退火气体，以固化隧道绝缘层图案的缺陷。

16. 发明授权

US07687860B2 Semiconductor device including impurity regions having different cross-sectional shapes 有权
标题翻译：包括具有不同横截面形状的杂质区域的半导体器件
公开(公告)号：US07687860B2
公开(公告)日：2010-03-30
申请号：US11425444
申请日：2006-06-21
申请人： Woon-Kyung Lee , Jeong-Hyuk Choi , Dong-Jun Lee , Jai-Hyuk Song
发明人： Woon-Kyung Lee , Jeong-Hyuk Choi , Dong-Jun Lee , Jai-Hyuk Song
IPC分类号： H01L21/8239
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/42324 , H01L29/42376 , H01L29/66825
摘要： There are provided a memory transistor having a select transistor with asymmetric gate electrode structure and an inverted T-shaped floating gates and a method for forming the same. A gate electrode of the select transistor adjacent to a memory transistor has substantially an inverted T-shaped figure, whereas the gate electrode of the select transistor opposite to the memory transistor has nearly a box-shaped figure. In order to form the floating gate of the memory transistor in shape of the inverted T, a region for the select transistor is closed when opening a region for the memory transistor.
摘要翻译：提供了一种存储晶体管，其具有具有不对称栅电极结构的选择晶体管和反向T形浮栅及其形成方法。与存储晶体管相邻的选择晶体管的栅电极具有大致倒T形图形，而与存储晶体管相对的选择晶体管的栅电极具有几乎一个盒形图形。为了以反相T的形式形成存储晶体管的浮置栅极，当打开存储晶体管的区域时，用于选择晶体管的区域闭合。

17. 发明授权

US07683422B2 Non-volatile memory devices with wraparound-shaped floating gate electrodes and methods of forming same 失效
标题翻译：具有环绕形状的浮栅电极的非易失性存储器件及其形成方法
公开(公告)号：US07683422B2
公开(公告)日：2010-03-23
申请号：US11464324
申请日：2006-08-14
申请人： Woon-Kyung Lee , Jeong-Hyuk Choi , Jai-Hyuk Song
发明人： Woon-Kyung Lee , Jeong-Hyuk Choi , Jai-Hyuk Song
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521
摘要： Non-volatile memory devices include memory cells therein with reduced cell-to-cell coupling capacitance. These memory cells include floating gate electrodes with open-ended wraparound shapes that operate to reduce the cell-to-cell coupling capacitance in a bit line direction, while still maintaining a high coupling ratio between control and floating gate electrodes within each memory cell.
摘要翻译：非易失性存储器件包括其中具有减小的单元到单元耦合电容的存储单元。这些存储单元包括具有开口环绕形状的浮动栅极电极，其操作以在位线方向上减小电池到电池耦合电容，同时仍保持每个存储单元内的控制和浮置栅电极之间的高耦合比。

18. 发明申请

US20080081413A1 Semiconductor memory devices and methods for forming the same 有权
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20080081413A1
公开(公告)日：2008-04-03
申请号：US11647671
申请日：2006-12-29
申请人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
发明人： Chang-Sub Lee , Jeong-Hyuk Choi , Woon-Kyung Lee , Jai-Hyuk Song , Dong-Yean Oh
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device can include select transistors and cell transistors on a semiconductor substrate. An insulation layer covers the select transistors and the cell transistors. The bit lines are in the insulation layer and are electrically connected to respective ones of the select transistors. The bit lines are arranged along at least two different parallel planes having different heights relative to the semiconductor substrate.
摘要翻译：半导体存储器件可以包括半导体衬底上的选择晶体管和单元晶体管。绝缘层覆盖选择晶体管和单元晶体管。位线在绝缘层中并且电连接到相应的选择晶体管。沿着相对于半导体衬底具有不同高度的至少两个不同的平行平面布置位线。

19. 发明申请

US20070190726A1 Semiconductor device and related fabrication method 有权
标题翻译：半导体器件及相关制造方法
公开(公告)号：US20070190726A1
公开(公告)日：2007-08-16
申请号：US11699990
申请日：2007-01-31
申请人： Jai-Hyuk Song , Jeong-Hyuk Choi , Woon-Kyung Lee
发明人： Jai-Hyuk Song , Jeong-Hyuk Choi , Woon-Kyung Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11541
摘要： Embodiments of the invention provide a semiconductor device and a related method of fabricating a semiconductor device. In one embodiment, the invention provides a semiconductor device comprising a first gate electrode comprising a lower silicon pattern and an upper silicon pattern and disposed on an active region of a semiconductor substrate, wherein the upper silicon pattern has the same crystal structure as the lower silicon pattern and the active region is defined by a device isolation layer. The semiconductor device further comprises a gate insulating layer disposed between the active region and the first gate electrode.
摘要翻译：本发明的实施例提供一种制造半导体器件的半导体器件和相关方法。在一个实施例中，本发明提供一种半导体器件，其包括第一栅电极，其包括下硅图案和上硅图案，并设置在半导体衬底的有源区上，其中上硅图案具有与下硅相同的晶体结构图案和有源区域由器件隔离层定义。半导体器件还包括设置在有源区和第一栅电极之间的栅极绝缘层。

20. 发明授权

US08324052B2 Methods of fabricating non-volatile memory devices including double diffused junction regions 有权
标题翻译：制造包括双扩散连接区域的非易失性存储器件的方法
公开(公告)号：US08324052B2
公开(公告)日：2012-12-04
申请号：US13010583
申请日：2011-01-20
申请人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
发明人： Dong-Yean Oh , Jai-Hyuk Song , Chang-Sub Lee , Chang-Hyun Lee , Hyun-Jae Kim
IPC分类号： H01L21/331
CPC分类号： H01L27/11521 , H01L21/26586 , H01L27/115 , H01L27/11524
摘要： A nonvolatile memory device includes a string selection gate and a ground selection gate on a semiconductor substrate, and a plurality of memory cell gates on the substrate between the string selection gate and the ground selection gate. First impurity regions extend into the substrate to a first depth between ones of the plurality of memory cell gates. Second impurity regions extend into the substrate to a second depth that is greater than the first depth between the string selection gate and a first one of the plurality of memory cell gates immediately adjacent thereto, and between the ground selection gate and a last one of the plurality of memory cell gates immediately adjacent thereto. Related fabrication methods are also discussed.
摘要翻译：非易失性存储器件包括半导体衬底上的串选择栅极和接地选择栅极，以及在串选择栅极和地选择栅极之间的衬底上的多个存储单元栅极。第一杂质区域延伸到衬底中到多个存储单元门之间的第一深度。第二杂质区域延伸到衬底中的第二深度，该第二深度大于串选择栅极与紧邻其之间的多个存储单元栅极中的第一深度之间以及在接地选择栅极和最后一个栅极选择栅极之间的第一深度与其紧邻的多个存储单元门。还讨论了相关的制造方法。

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