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11. 发明申请

US20130105941A1 SEMICONDUCTOR DEVICE INCLUDING IN WAFER INDUCTORS, RELATED METHOD AND DESIGN STRUCTURE 有权
标题翻译：包括波导电感的半导体器件，相关方法和设计结构
公开(公告)号：US20130105941A1
公开(公告)日：2013-05-02
申请号：US13282123
申请日：2011-10-26
申请人： Daniel S. Vanslette , John J. Ellis-Monaghan , Renata A. Camillo-Castillo , Robert M. Rassel
发明人： Daniel S. Vanslette , John J. Ellis-Monaghan , Renata A. Camillo-Castillo , Robert M. Rassel
IPC分类号： H01L23/48 , G06F17/50 , H01L21/02
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5227 , H01L27/016 , H01L27/0694 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first set of trenches formed in a first surface of the substrate; a second set of trenches formed in a second surface of the substrate; and at least one through silicon via connecting the first set of trenches and the second set of trenches.
摘要翻译：一种集成电路（IC）及其制造方法。在一个实施例中，IC包括：衬底; 形成在所述基板的第一表面中的第一组沟槽; 形成在所述基板的第二表面中的第二组沟槽; 以及通过连接第一组沟槽和第二组沟槽的至少一个穿硅。

12. 发明申请

US20130084476A1 FUSE FOR THREE DIMENSIONAL SOLID-STATE BATTERY 有权
标题翻译：三维固态电池的保险丝
公开(公告)号：US20130084476A1
公开(公告)日：2013-04-04
申请号：US13252366
申请日：2011-10-04
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01M10/42 , H01M10/04
CPC分类号： H01M10/04 , H01M2/204 , H01M2/24 , H01M2/34 , H01M4/767 , H01M10/02 , H01M10/052 , H01M10/0562 , H01M10/42 , Y02E60/12 , Y10T29/49108
摘要： A solid-state battery structure having a plurality of battery cells formed in a substrate, method of manufacturing the same and design structure thereof are provided. The battery structure includes a patterned cathode electrode layer formed upon the substrate and structured to form a plurality of sub-arrays of the battery cells. The battery structure further includes a plurality of fuse wires structured to interconnect at least two adjacent sub-arrays. At least one of the plurality of fuse wires is structured to be blown to disconnect an interconnection having a defective sub-array. Advantageously, the plurality of fuse wires is an integral part of the battery structure.
摘要翻译：提供了具有形成在基板中的多个电池单元的固态电池结构，其制造方法和设计结构。电池结构包括形成在基板上并构造成形成电池单元的多个子阵列的图案化阴极电极层。电池结构还包括构造成互连至少两个相邻子阵列的多个熔丝。多个熔丝中的至少一个被构造成被吹塑以断开具有缺陷子阵列的互连。有利的是，多个熔丝是电池结构的组成部分。

13. 发明授权

US08383443B2 Non-uniform gate dielectric charge for pixel sensor cells and methods of manufacturing 有权
公开(公告)号：US08383443B2
公开(公告)日：2013-02-26
申请号：US12780193
申请日：2010-05-14
申请人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , Andres Bryant , William F. Clark, Jr. , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L21/00
CPC分类号： H01L31/02 , H01L27/14614 , H01L27/14689
摘要： A non-uniform gate dielectric charge for pixel sensor cells, e.g., CMOS optical imagers, and methods of manufacturing are provided. The method includes forming a gate dielectric on a substrate. The substrate includes a source/drain region and a photo cell collector region. The method further includes forming a non-uniform fixed charge distribution in the gate dielectric. The method further includes forming a gate structure on the gate dielectric.

14. 发明授权

US08232215B2 Spacer linewidth control 有权
标题翻译：间隔线宽控制
公开(公告)号：US08232215B2
公开(公告)日：2012-07-31
申请号：US12622557
申请日：2009-11-20
申请人： James A. Culp , Jeffrey P. Gambino , John J. Ellis-Monaghan , Kirk D. Peterson , Jed H. Rankin
发明人： James A. Culp , Jeffrey P. Gambino , John J. Ellis-Monaghan , Kirk D. Peterson , Jed H. Rankin
IPC分类号： H01L21/302
CPC分类号： H01L21/31144
摘要： A method for forming a plurality of variable linewidth spacers adjoining a plurality of uniformly spaced topographic features uses a conformal resist layer upon a spacer material layer located over the plurality of uniformly spaced topographic features. The conformal resist layer is differentially exposed and developed to provide a differential thickness resist layer that is used as a sacrificial mask when forming the variable linewidth spacers. A method for forming uniform linewidth spacers adjoining narrowly spaced topographic features and widely spaced topographic features over the same substrate uses a masked isotropic etching of a variable thickness spacer material layer to provide a more uniform partially etched spacer material layer, followed by an unmasked anisotropic etching of the partially etched spacer material layer. A related method for forming the uniform linewidth spacers uses a two-step anisotropic etch method that includes at least one masking process step.
摘要翻译：用于形成邻接多个均匀间隔的地形特征的多个可变线宽间隔物的方法在位于多个均匀间隔的地形特征之上的间隔物材料层上使用共形抗蚀剂层。保形抗蚀剂层被差异地曝光和显影以提供在形成可变线宽间隔物时用作牺牲掩模的差分厚度抗蚀剂层。用于形成均匀线宽间隔物的方法，其邻接狭窄间隔的地形特征和在相同基底上的宽间隔的地形特征，使用可变厚度间隔物材料层的掩蔽各向同性蚀刻，以提供更均匀的部分蚀刻的间隔物材料层，随后是未掩模的各向异性蚀刻的部分蚀刻的间隔材料层。用于形成均匀线宽间隔物的相关方法使用包括至少一个掩模处理步骤的两步各向异性蚀刻方法。

15. 发明申请

US20120149200A1 NITRIDE ETCH FOR IMPROVED SPACER UNIFORMITY 失效
标题翻译：用于改进间隔均匀的氮化层
公开(公告)号：US20120149200A1
公开(公告)日：2012-06-14
申请号：US12966432
申请日：2010-12-13
申请人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
发明人： James A. Culp , John J. Ellis-Monaghan , Jeffrey P. Gambino , Kirk D. Peterson , Jed H. Rankin , Christa R. Willets
IPC分类号： H01L21/311
CPC分类号： H01L21/31116 , H01L21/28035 , H01L21/76237 , H01L21/823425 , H01L21/823468 , H01L21/823481 , H01L29/78
摘要： A method of forming dielectric spacers including providing a substrate comprising a first region having a first plurality of gate structures and a second region having a second plurality of gate structures and at least one oxide containing material or a carbon containing material. Forming a nitride containing layer over the first region having a thickness that is less than the thickness of the nitride containing layer that is present in the second region. Forming dielectric spacers from the nitride containing layer on the first plurality the second plurality of gate structures. The at least one oxide containing material or carbon containing material accelerates etching in the second region so that the thickness of the dielectric spacers in the first region is substantially equal to the thickness of the dielectric spacers in the second region of the substrate.
摘要翻译：一种形成电介质间隔物的方法，包括提供包括具有第一多个栅极结构的第一区域和具有第二多个栅极结构的第二区域和至少一种含氧化物的材料或含碳材料的衬底。在第一区域上形成厚度小于存在于第二区域中的含氮化物层的厚度的含氮化物层。在第一多个第二多个栅极结构上从氮化物含有层形成电介质间隔物。所述至少一种含氧化物的材料或含碳材料加速了第二区域中的蚀刻，使得第一区域中的电介质间隔物的厚度基本上等于衬底的第二区域中的电介质间隔物的厚度。

16. 发明授权

US08158453B2 Methods of forming silicide strapping in imager transfer gate device 有权
标题翻译：在成像器传输门装置中形成硅化物带的方法
公开(公告)号：US08158453B2
公开(公告)日：2012-04-17
申请号：US12699419
申请日：2010-02-03
申请人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
发明人： James W. Adkisson , John J. Ellis-Monaghan , R. Michael Guidash , Mark D. Jaffe , Edward T. Nelson , Richard J. Rassel , Charles V. Stancampiano
IPC分类号： H01L21/336
CPC分类号： H01L27/14609 , H01L27/14643 , H01L27/14689
摘要： A CMOS active pixel sensor (APS) cell structure having dual workfunction transfer gate device and method of fabrication. The transfer gate device comprises a dielectric layer formed on a substrate and a dual workfunction gate conductor layer formed on the dielectric layer comprising a first conductivity type doped region and an abutting second conductivity type doped region. The transfer gate device defines a channel region where charge accumulated by a photosensing device is transferred to a diffusion region. A silicide structure is formed atop the dual workfunction gate conductor layer for electrically coupling the first and second conductivity type doped regions. In one embodiment, the silicide contact is smaller in area dimension than an area dimension of said dual workfunction gate conductor layer. Presence of the silicide strap prevents the diodic behavior from allowing one or the other side of the gate to float to an indeterminate voltage.
摘要翻译：具有双功能转移栅极器件和制造方法的CMOS有源像素传感器（APS）单元结构。传输栅极器件包括形成在衬底上的电介质层和形成在包括第一导电类型掺杂区和邻接第二导电类型掺杂区的电介质层上的双功函数栅导体层。传输门装置限定了由光敏装置累积的电荷被传送到扩散区的沟道区。在双功函数栅极导体层顶部形成硅化物结构，用于电耦合第一和第二导电类型掺杂区域。在一个实施例中，硅化物接触面积尺寸小于所述双功函数栅极导体层的面积尺寸。硅化物带的存在防止了双极性行为允许栅极的一侧或另一侧浮动到不确定的电压。

17. 发明授权

US08138534B2 Anti-reflection structures for CMOS image sensors 有权
标题翻译： CMOS图像传感器的防反射结构
公开(公告)号：US08138534B2
公开(公告)日：2012-03-20
申请号：US12770349
申请日：2010-04-29
申请人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
发明人： James W. Adkisson , John J. Ellis-Monaghan , Jeffrey P. Gambino , Charles F. Musante
IPC分类号： H01L31/10 , H01L31/112
CPC分类号： H01L31/103 , H01L24/05 , H01L24/73 , H01L27/14603 , H01L27/1462 , H01L27/14627 , H01L27/14629 , H01L27/1464 , H01L27/14643 , H01L31/02165 , H01L31/0236 , H01L2224/04042 , H01L2224/05 , H01L2224/32225 , H01L2224/48227 , H01L2224/48464 , H01L2224/4847 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/12043 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/3025 , Y02E10/50 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： Optical structures having an array of protuberances between two layers having different refractive indices are provided. The array of protuberances has vertical and lateral dimensions less than the wavelength range of lights detectable by a photodiode of a CMOS image sensor. The array of protuberances provides high transmission of light with little reflection. The array of protuberances may be provided over a photodiode, in a back-end-of-line interconnect structure, over a lens for a photodiode, on a backside of a photodiode, or on a window of a chip package.
摘要翻译：提供了具有不同折射率的两层之间的突起阵列的光学结构。突起阵列具有小于由CMOS图像传感器的光电二极管可检测的光的波长范围的垂直和侧向尺寸。突起的阵列提供了很少的反射光的高透射率。突起阵列可以设置在光电二极管上，后端行互连结构中，用于光电二极管的透镜，光电二极管的背面或芯片封装的窗口上。

18. 发明授权

US08009216B2 Pixel sensor cell with frame storage capability 有权
公开(公告)号：US08009216B2
公开(公告)日：2011-08-30
申请号：US12174289
申请日：2008-07-16
申请人： James W. Adkisson , John J. Ellis-Monaghan , Rajendran Krishnasamy , Solomon Mulugeta , Charles F. Musante , Richard J. Rassel
发明人： James W. Adkisson , John J. Ellis-Monaghan , Rajendran Krishnasamy , Solomon Mulugeta , Charles F. Musante , Richard J. Rassel
IPC分类号： H04N3/14 , H04N5/335
CPC分类号： H04N5/37452 , H04N5/2355
摘要： A set of frame transfer transistors are provided between a hold gate transistor and a transfer gate transistor of a CMOS image sensor to enable storage of charge generate in the photosensitive diode after exposure. The readout of the charges from the set of frame transfer transistors may be performed after a plurality of exposures of the CMOS image sensor, between each of which charges are shifted toward the transfer gate transistor within the set of frame transfer transistors. Useful operation modes are enabled including a burst mode operation for rapid capture of successive images and high dynamic range operations in which multiple images are taken with different exposure times or a large capacitance is provided by ganging the diffusions of the set of frame transfer transistors.

19. 发明授权

US07935560B2 Imagers having electrically active optical elements 有权
标题翻译：具有电活动光学元件的成像器
公开(公告)号：US07935560B2
公开(公告)日：2011-05-03
申请号：US11850801
申请日：2007-09-06
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak
IPC分类号： H01L21/00
CPC分类号： H01L27/14636 , H04N5/374
摘要： A method of fabricating a CMOS image sensor comprising an array of active pixel cells. Each active pixel cell includes a substrate; a photosensing device formed at or below a substrate surface for collecting charge carriers in response to incident light; and, one or more light transmissive conductive wire structures formed above the photosensing device, the one or more conductive wire structures being located in an optical path above the photosensing device. The formed light transmissive conductive wire structures provide both an electrical and optical function. An optical function is provided by tailoring the thickness of the conductive wire layer to filter light according to a pixel color scheme. Alternately, the light transmissive conductive wire structures may be formed as a microlens structure providing a light focusing function. Electrical functions for the conductive wire layer include use as a capacitor plate, as a resistor or as an interconnect.
摘要翻译：一种制造包括有源像素单元阵列的CMOS图像传感器的方法。每个有源像素单元包括衬底; 形成在基板表面处或下方的光敏装置，用于响应于入射光收集电荷载体; 以及形成在光敏器件上方的一个或多个透光导线结构，所述一个或多个导电线结构位于光敏器件上方的光路中。形成的透光导线结构提供电和光学功能。通过根据像素配色方案调整导线层的厚度以过滤光，提供光学功能。或者，透光导线结构可以形成为提供光聚焦功能的微透镜结构。用于导线层的电气功能包括用作电容器板，电阻器或互连件。

20. 发明授权

US07915056B2 Image sensor monitor structure in scribe area 失效
标题翻译：图像传感器监控结构在划片区域
公开(公告)号：US07915056B2
公开(公告)日：2011-03-29
申请号：US12051868
申请日：2008-03-20
申请人： John J. Ellis-Monaghan , Mark D. Jaffe , Sambasivan Narayan , Anthony J. Perri , Richard J. Rassel , Tian Xia
发明人： John J. Ellis-Monaghan , Mark D. Jaffe , Sambasivan Narayan , Anthony J. Perri , Richard J. Rassel , Tian Xia
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/2884 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.
摘要翻译：设计并制造了包括位于划线区域中的半导体芯片和测试结构的半导体管芯。测试结构包括互补金属氧化物半导体（CMOS）图像传感器的阵列，其与在半导体芯片中的另一阵列中使用并具有较大阵列尺寸的CMOS图像传感器具有相同的类型。通过提供CMOS图像传感器的取向在两个阵列之间匹配的设计结构，在设计阶段提供了这种测试结构。测试结构通过在半导体芯片上的最终测试之前的在线测试来提供对制造工艺的有效和准确的监控。

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