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11. 发明授权

US06928011B2 Electrical fuse control of memory slowdown 有权
标题翻译：电熔丝控制内存减速
公开(公告)号：US06928011B2
公开(公告)日：2005-08-09
申请号：US10630963
申请日：2003-07-30
申请人： Manjeri Krishnan , Bryan Sheffield , Joel J. Graber , Duy-Loan Le , Sanjive Agarwala
发明人： Manjeri Krishnan , Bryan Sheffield , Joel J. Graber , Duy-Loan Le , Sanjive Agarwala
IPC分类号： G11C29/50 , G11C29/00
CPC分类号： G11C29/027 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.
摘要翻译：电气保险丝（eFuse）被应用于存储器性能调整的任务，以通过不需要额外的处理步骤和昂贵的设备来改进早期保险丝技术。标准电熔丝（eFuse）硬件链提供了软测试功能，其中可以在实际编程保险丝之前测试存储器减速的影响。因此，电熔丝提供非常有效的非易失性方法，以通过存储器修整来匹配逻辑存储器接口，大大降低成本和所涉及的周期时间。

12. 发明申请

US20050169078A1 Tracking circuit enabling quick/accurate retrieval of data stored in a memory array 有权
标题翻译：跟踪电路，可快速/准确地检索存储在存储器阵列中的数据
公开(公告)号：US20050169078A1
公开(公告)日：2005-08-04
申请号：US10768131
申请日：2004-02-02
申请人： Suresh Balasubramanian , Stephen Spriggs , Bryan Sheffield , Mohan Mishra
发明人： Suresh Balasubramanian , Stephen Spriggs , Bryan Sheffield , Mohan Mishra
IPC分类号： G11C7/02 , G11C7/06 , G11C7/08
CPC分类号： G11C7/227 , G11C7/067 , G11C7/08 , G11C2207/063
摘要： An actual sense amplifier senses a signal received on a bit line to generate a bit, and a latch latches the bit at a time point specified by a latch enable signal. A tracking circuit generates the latch enable signal in an appropriate time window. The tracking circuit may contain a dummy sense amplifier implemented similar to the actual sense amplifier and a dummy column from which the actual sense amplifier senses a signal received upon accessing the dummy memory array. The latch enable signal may be generated after the dummy sense amplifier generates a bit representing the sensed signal. The time taken by the dummy sense amplifier to generate the bit depends on the load offered by the dummy memory array. Accordingly, the dummy memory array is designed to offer sufficient load to ensure that the latch enable signal is generated in an appropriate time window.
摘要翻译：实际的感测放大器感测在位线上接收到的信号以产生位，并且锁存器在由锁存器使能信号指定的时间点锁存该位。跟踪电路在适当的时间窗口中产生锁存使能信号。跟踪电路可以包含类似于实际读出放大器的虚拟读出放大器和一个虚拟列，实际读出放大器从该虚拟列感测在访问伪存储器阵列时接收到的信号。可以在虚拟读出放大器产生表示感测信号的位之后产生锁存使能信号。虚拟读出放大器产生位的时间取决于虚拟存储器阵列提供的负载。因此，虚拟存储器阵列被设计成提供足够的负载以确保在适当的时间窗口中产生锁存使能信号。

13. 发明申请

US20050169077A1 Sense amplifier for a memory array 有权
标题翻译：用于存储器阵列的感应放大器
公开(公告)号：US20050169077A1
公开(公告)日：2005-08-04
申请号：US10768098
申请日：2004-02-02
申请人： Suresh Balasubramanian , Stephen Spriggs , Bryan Sheffield , Mohan Mishra
发明人： Suresh Balasubramanian , Stephen Spriggs , Bryan Sheffield , Mohan Mishra
IPC分类号： G11C7/00 , G11C7/06
CPC分类号： G11C7/227 , G11C7/067 , G11C2207/063
摘要： A sense amplifier which senses whether current is present on a bit line, and generates one logical value if current is present and another logical value if current is not present. As the sense amplifier can be implemented to generate such logical values with a current signal of low strength, memory arrays with correspondingly low drive strength can be implemented. As a result, memory systems which consume minimal power and having high density can be provided. In addition, as the sense amplifiers can operate without any reference signals, the implementation of sense amplifiers may be simplified.
摘要翻译：感测放大器，其感测电流是否存在于位线上，并且如果存在电流并且如果电流不存在则产生一个逻辑值，并且如果电流不存在则产生另一个逻辑值。由于可以实现读出放大器以用低强度的电流信号生成这样的逻辑值，所以可以实现具有相应低的驱动强度的存储器阵列。结果，可以提供消耗最小功率并具有高密度的存储器系统。此外，由于读出放大器可以在没有参考信号的情况下工作，因此可以简化读出放大器的实现。

14. 发明授权

US08093716B2 Contact fuse which does not touch a metal layer 有权
标题翻译：接触不接触金属层的保险丝
公开(公告)号：US08093716B2
公开(公告)日：2012-01-10
申请号：US11192825
申请日：2005-07-29
申请人： Robert L. Pitts , Bryan Sheffield , Roger Griesmer , Joe McPherson
发明人： Robert L. Pitts , Bryan Sheffield , Roger Griesmer , Joe McPherson
IPC分类号： H01L23/34
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor device fuse, comprising a metal layer and a first semiconductor layer that electrically couples the metal layer to a fuse layer, wherein the fuse layer is spaced apart from the metal layer. The semiconductor device fuse further comprises a second semiconductor layer that forms a blow junction interface with the fuse layer. The blow junction interface is configured to form an open circuit when a predefined power is transmitted through the second semiconductor layer to the fuse layer.
摘要翻译：本发明提供了一种半导体器件熔丝，其包括金属层和将金属层电耦合到熔丝层的第一半导体层，其中熔丝层与金属层间隔开。半导体器件熔丝进一步包括形成与熔丝层的熔结接口的第二半导体层。当预定义的功率通过第二半导体层透射到熔丝层时，该熔接结界面被配置为形成开路。

15. 发明授权

US07230868B2 Stable source-coupled sense amplifier 有权
标题翻译：稳定的源极耦合读出放大器
公开(公告)号：US07230868B2
公开(公告)日：2007-06-12
申请号：US11191709
申请日：2005-07-28
申请人： Sudhir K. Madan , Bryan Sheffield
发明人： Sudhir K. Madan , Bryan Sheffield
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C11/22
摘要： An amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706, 708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726), and third pull down transistor between the first and second input terminals. The control gates of the first, second and third pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.
摘要翻译：放大器电路包括放大器部分（700），均衡部分（770）和激活部分（720）。放大器部分的P沟道晶体管（702,704）耦合到电源端子（802）。放大器部分的N沟道晶体管（706,708）分别耦合在P沟道晶体管和第一和第二输入端（760,762）之间。在激活部分中，第一和第二下拉晶体管（722,724）分别耦合在第一和第二输入端之间，第二电源端（726）和第三和第二输入端之间的第三下拉晶体管。第一，第二和第三下拉晶体管的控制栅彼此耦合。在操作中，施加到第一和第二输入端的电压信号被N沟道晶体管放大。然后施加控制信号以将第一和第二输入端耦合到电源电压。

16. 发明申请

US20050247995A1 Metal contact fuse element 审中-公开
标题翻译：金属接触保险丝元件
公开(公告)号：US20050247995A1
公开(公告)日：2005-11-10
申请号：US10840444
申请日：2004-05-06
申请人： Robert Pitts , Bryan Sheffield , Roger Greismer
发明人： Robert Pitts , Bryan Sheffield , Roger Greismer
IPC分类号： H01L21/44 , H01L21/768 , H01L21/82 , H01L23/525 , H01L29/00
CPC分类号： H01L21/76892 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Severable metal contacts (42) are provided for use within a circuit in a semiconductor device whereby an open circuit may be formed by the application of a pre-selected voltage or current. Preferred embodiments and associated methods are described in which a semiconductor device fuse (30) includes first and second conductors (36, 38) having first and second metallic contacts (40, 42) operably coupled to a conductive layer (34) for forming an electrical path. At least one of the metallic contacts (42) is configured to operate as a metallic fuse element adapted to form an open circuit (44) in response to reaching a pre-selected voltage threshold or current. Preferred embodiments of the invention are described in which it is used for programmable read only memory (PROM) elements.
摘要翻译：提供可切断的金属触点（42）用于在半导体器件的电路内使用，由此可以通过施加预先选择的电压或电流来形成开路。描述了优选实施例和相关联的方法，其中半导体器件熔丝（30）包括具有可操作地耦合到导电层（34）的第一和第二金属触点（40,42）的第一和第二导体（36,38），用于形成电路径。金属触点（42）中的至少一个被配置为作为适于响应于达到预先选择的电压阈值或电流而形成开路（44）的金属熔丝元件而工作。描述了本发明的优选实施例，其中它用于可编程只读存储器（PROM）元件。

17. 发明申请

US20050213411A1 Electrical fuse control of memory slowdown 有权
公开(公告)号：US20050213411A1
公开(公告)日：2005-09-29
申请号：US11121387
申请日：2005-05-03
申请人： Manjeri Krishnan , Bryan Sheffield , Joel Graber , Duy-Loan Le , Sanjive Agarwala
发明人： Manjeri Krishnan , Bryan Sheffield , Joel Graber , Duy-Loan Le , Sanjive Agarwala
IPC分类号： G11C29/50 , G11C5/00
CPC分类号： G11C29/027 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.

18. 发明申请

US20050120283A1 CAM test structures and methods therefor 有权
标题翻译： CAM测试结构及其方法
公开(公告)号：US20050120283A1
公开(公告)日：2005-06-02
申请号：US10635348
申请日：2003-08-06
申请人： George Harris , Bryan Sheffield , Dwayne Ward
发明人： George Harris , Bryan Sheffield , Dwayne Ward
IPC分类号： G11C29/02 , G11C29/24 , G11C29/00
CPC分类号： G11C29/12015 , G11C15/00 , G11C29/02 , G11C29/24
摘要： Configurations and methods that enable the testing of CAM-specific circuitry, even if the memory is defective, are implemented by utilizing various test modes. Accordingly, the CAM can be debugged to isolate memory failures from priority encoder failures, which significantly reduces the need for design changes. The present invention provides the ability to test the CAM functions very efficiently, thereby reducing the test time.
摘要翻译：通过使用各种测试模式，即使存储器有缺陷，也能够实现CAM专用电路测试的配置和方法。因此，CAM可以进行调试，以将存储器故障与优先编码器故障隔离开来，这显着地减少了对设计变更的需求。本发明提供了非常有效地测试CAM功能的能力，从而减少测试时间。

19. 发明申请

US20050099202A1 METHOD OF TESTING AN INTEGRATED CIRCUIT AND AN INTEGRATED CIRCUIT TEST APPARATUS 有权
标题翻译：集成电路和集成电路测试装置的测试方法
公开(公告)号：US20050099202A1
公开(公告)日：2005-05-12
申请号：US10704858
申请日：2003-11-10
申请人： Theodore Houston , Bryan Sheffield
发明人： Theodore Houston , Bryan Sheffield
IPC分类号： G01R31/28 , G01R31/30 , G11C29/04 , G11C29/56 , G01R31/26
CPC分类号： G01R31/3004 , G01R31/2879 , G11C11/41 , G11C29/04 , G11C29/56
摘要： A method of testing an Integrated Circuit (IC) and an IC test apparatus is provided. In one embodiment, the method of testing includes (1) applying a voltage to the IC that is not a normal operating voltage of the IC and (2) temporarily biasing a well voltage of transistors in the IC allowing screening for the normal operating voltage.
摘要翻译：提供一种测试集成电路（IC）和IC测试装置的方法。在一个实施例中，测试方法包括（1）向IC施加不是IC的正常工作电压的电压，以及（2）暂时偏置IC中的晶体管的阱电压，从而筛选正常工作电压。

20. 发明申请

US20050007861A1 System for reducing row periphery power consumption in memory devices 有权
标题翻译：用于减少存储器件中的行周边功耗的系统
公开(公告)号：US20050007861A1
公开(公告)日：2005-01-13
申请号：US10618473
申请日：2003-07-11
申请人： Xiaowei Deng , Theodore Houston , Bryan Sheffield
发明人： Xiaowei Deng , Theodore Houston , Bryan Sheffield
IPC分类号： G11C8/08 , G11C11/417 , G11C8/00
CPC分类号： G11C8/08 , G11C11/417
摘要： The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.
摘要翻译：本发明提供了一种用于减少半导体存储器件中的行周边功耗的系统，特别是在睡眠模式操作期间。根据本发明的存储器件（100）在存储器单元行之前具有一行（106）存储单元和驱动器电路（102）。本发明提供了一种在靠近该行存储器单元的驱动器电路内实例化的介入电路（114）。在介入电路之前的驱动器电路（108,110）掉电的同时，介入电路被操作以将该行存储器单元保持在期望的状态。

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