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11. 发明授权

US07447818B2 System and method for controlling remote console functionality assist logic 有权
标题翻译：用于控制远程控制台功能的系统和方法辅助逻辑
公开(公告)号：US07447818B2
公开(公告)日：2008-11-04
申请号：US10716144
申请日：2003-11-18
申请人： Theodore F. Emerson , Siamak Tavallaei , John V. Butler
发明人： Theodore F. Emerson , Siamak Tavallaei , John V. Butler
IPC分类号： G06F15/16 , G06F3/00
CPC分类号： G06F11/2294
摘要： A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.
摘要翻译：计算机系统，例如设置在企业中的服务器，可从远程终端访问用于远程管理应用。计算机系统包括用于实现从远程终端发送和接收信号的远程控制台功能辅助逻辑结构。远程控制台功能辅助逻辑结构由专用处理器控制，专用处理器响应于远程管理应用从其接收中断。处理器还可以控制在计算机系统中提供的一个或多个外围设备，其中受控的外围设备或设备从处理器的上游或下游设置。

12. 发明授权

US06792490B2 System and method for hiding peripheral devices from a host processor in a computer system 失效
标题翻译：用于在计算机系统中从主处理器隐藏外围设备的系统和方法
公开(公告)号：US06792490B2
公开(公告)日：2004-09-14
申请号：US09991058
申请日：2001-11-16
申请人： Siamak Tavallaei
发明人： Siamak Tavallaei
IPC分类号： G06F1314
CPC分类号： G06F13/4027
摘要： A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. A plurality of I/O bus signals are supplied to the device blocking module for determining which bus master owns the I/O bus in order to initiate a bus cycle. If the bus cycle is about to be commenced on behalf of the host processor and its OS, an enable signal associated with the selected peripheral device is negated until the cycle is completed. If, on the other hand, the bus cycle is initiated by the IOP, the enable signal is asserted for the duration of the transaction, which signal, otherwise, remains in a negated state.
摘要翻译：具有智能输入/输出架构的计算机系统具有用于隐藏外围设备的至少一部分的动态设备阻塞机制。计算机系统包括用于执行主机操作系统的主机处理器，设置在主机总线上的主机处理器，经由主机到总线桥接器可操作地耦合到主机总线的输入/输出（I / O）总线，以及可操作地连接到I / O总线的用于在由IOP资源控制的I / O事务中传送数据的多个外围设备。多个I / O总线信号被提供给器件阻塞模块，用于确定哪个总线主机拥有I / O总线以便启动总线周期。如果总线周期即将代表主处理器及其OS开始，则与选定的外围设备相关联的使能信号被否定，直到该周期完成。另一方面，如果由IOP启动总线周期，则在交易持续时间内使能使能信号，否则，该信号保持在否定状态。

13. 发明授权

US06747563B2 Removable memory cartridge system for use with a server or other processor-based device 有权
标题翻译：可移动内存盒系统，用于与服务器或其他基于处理器的设备配合使用
公开(公告)号：US06747563B2
公开(公告)日：2004-06-08
申请号：US10437567
申请日：2003-05-14
申请人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
发明人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
IPC分类号： G08B2300
CPC分类号： G06F13/4081 , G06F13/409
摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.
摘要翻译：一种基于处理器的设备，其具有通过杠杆系统固定在底盘内的多个存储器盒。基于处理器的设备包括用于指示存储器系统操作条件的指示系统。当从基于处理器的设备移除存储器盒时，每个存储器盒具有保护组件以保护存储器盒内的存储器元件。基于处理器的设备是可操作的，使得可以从基于处理器的设备移除至少一个存储盒，而不影响基于处理器的设备的操作。

14. 发明授权

US06742066B2 System and method for controlling remote console functionality assist logic 有权
标题翻译：用于控制远程控制台功能的系统和方法辅助逻辑
公开(公告)号：US06742066B2
公开(公告)日：2004-05-25
申请号：US10108106
申请日：2002-03-27
申请人： Theodore F. Emerson , Siamak Tavallaei , John V. Butler
发明人： Theodore F. Emerson , Siamak Tavallaei , John V. Butler
IPC分类号： G06F1516
CPC分类号： G06F11/2294
摘要： A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.
摘要翻译：计算机系统，例如设置在企业中的服务器，可从远程终端访问用于远程管理应用。计算机系统包括用于实现从远程终端发送和接收信号的远程控制台功能辅助逻辑结构。远程控制台功能辅助逻辑结构由专用处理器控制，专用处理器响应于远程管理应用从其接收中断。处理器还可以控制在计算机系统中提供的一个或多个外围设备，其中受控的外围设备或设备从处理器的上游或下游设置。

15. 发明授权

US6098143A Remote server management device 失效
标题翻译：远程服务器管理设备
公开(公告)号：US6098143A
公开(公告)日：2000-08-01
申请号：US105725
申请日：1998-06-25
申请人： Brian Humpherys , John Butler , Siamak Tavallaei , Theodore F. Emerson , Doron Chosnek
发明人： Brian Humpherys , John Butler , Siamak Tavallaei , Theodore F. Emerson , Doron Chosnek
IPC分类号： G06F15/16
CPC分类号： G06F13/24 , H04N21/226 , H04N21/24 , H04N21/241 , H04N21/25
摘要： A computer system includes a bus, remote console logic, a remote server management device, and an interrupt routing switch. The bus has a first interrupt line. The remote console logic has a second interrupt line and is coupled to the bus. The remote console logic is adapted to monitor video transactions present on the bus. The video transactions include video data. The remote console logic is further adapted to store the video data and provide an interrupt signal on the second interrupt line if the amount of stored video data reaches a predetermined threshold. The remote server management device is coupled to the bus and the first interrupt line. The interrupt routing switch is coupled to the first interrupt line and the second interrupt line and adapted to couple the second interrupt line to the first interrupt line. A method for capturing video transactions includes coupling a first interrupt line of a buffer to a shared interrupt line of a bus. Video transactions occurring on the bus are snooped. The video transactions include video data. At least a portion of the video data is stored in the buffer. An interrupt signal is generated on the first interrupt line when the amount of data in the buffer reaches a predetermined threshold. The interrupt signal is received on the shared interrupt line in a remote server management device having memory. At least a portion of the video data is stored in the memory in response to the interrupt signal.
摘要翻译：计算机系统包括总线，远程控制台逻辑，远程服务器管理装置和中断路由交换机。总线有一条第一条中断线。远程控制台逻辑具有第二个中断线，并连接到总线。远程控制台逻辑适用于监视总线上存在的视频事务。视频交易包括视频数据。远程控制台逻辑还适于存储视频数据，并且如果存储的视频数据量达到预定阈值，则在第二中断线上提供中断信号。远程服务器管理设备耦合到总线和第一中断线。中断路由开关耦合到第一中断线和第二中断线，并且适于将第二中断线耦合到第一中断线。一种用于捕获视频事务的方法包括将缓冲器的第一中断线耦合到总线的共享中断线。公交车上发生的视频事件被窥探。视频交易包括视频数据。视频数据的至少一部分被存储在缓冲器中。当缓冲器中的数据量达到预定阈值时，在第一中断线上产生中断信号。在具有存储器的远程服务器管理设备中的共享中断线路上接收到中断信号。响应于中断信号，视频数据的至少一部分被存储在存储器中。

16. 发明授权

US5938751A Bus ring-back and voltage over-shoot reduction techniques coupled with hot-pluggability 失效
标题翻译：总线回铃和电压过拍减少技术加上热插拔
公开(公告)号：US5938751A
公开(公告)日：1999-08-17
申请号：US912092
申请日：1997-08-15
申请人： Siamak Tavallaei , Joseph P. Miller
发明人： Siamak Tavallaei , Joseph P. Miller
IPC分类号： G06F3/00 , G06F13/00 , G06F13/40
CPC分类号： G06F13/4081
摘要： A bus ring-back and voltage over-shoot reduction apparatus with capability for rendering an expansion slot of a computer system hot-pluggable, wherein a logic gate controls a switching element so that when the element is turned on, the input and output (I/O) nodes of the element are in a low ohmic conductive relationship. One of the I/O nodes is coupled to an expansion card whereas the other node is coupled to a bus to which the expansion slot is connected. The apparatus operates as a level shifter wherein the output node voltage follows the input node voltage until pinch-off such that the output voltage remains substantially stable thereafter. The apparatus also isolates the expansion card from the bus when the system is running or during the powering up of the card.
摘要翻译：一种具有能够呈现计算机系统的可插拔的计算机系统的扩展槽的总线环回和电压过拍还原装置，其中逻辑门控制开关元件，使得当元件被接通时，输入和输出（I / O）节点处于低欧姆导电关系。 I / O节点中的一个耦合到扩展卡，而另一个节点耦合到扩展槽连接到的总线。该装置作为电平转换器工作，其中输出节点电压跟随输入节点电压直到夹断，使得输出电压在此之后保持基本稳定。当系统运行或卡上电时，该设备还将扩展卡与总线隔离开来。

17. 发明授权

US5909584A Power interlock with fault indicators for computer system 失效
标题翻译：电源互锁与计算机系统的故障指示灯
公开(公告)号：US5909584A
公开(公告)日：1999-06-01
申请号：US911250
申请日：1997-08-15
申请人： Siamak Tavallaei , Robert F. Olson
发明人： Siamak Tavallaei , Robert F. Olson
IPC分类号： G06F1/18 , G06F1/26 , G06F13/00 , H01H9/20
CPC分类号： G06F1/189 , Y10T307/944
摘要： The invention relates to a computer system having a chassis with an access door allowing a user to access the computer circuitry. The computer circuitry has a plurality of critical circuit boards and an interlock circuit routed through connectors and cables associated with the critical circuitry. If any of the connectors are not connected or connected improperly the main power is prevented from turning on or the main power to the computer is turned off and auxiliary power is used to power indicator lights which aid a user determine which connector is not connected or improperly connected.
摘要翻译：本发明涉及一种计算机系统，其具有带有允许用户访问计算机电路的访问门的机架。计算机电路具有多个关键电路板和通过与关键电路相关联的连接器和电缆布线的互锁电路。如果任何连接器未连接或连接不正确，则防止主电源打开或关闭计算机的主电源，并使用辅助电源为指示灯供电，以帮助用户确定哪个连接器未连接或不正确连接的。

18. 发明授权

US5864653A PCI hot spare capability for failed components 失效
公开(公告)号：US5864653A
公开(公告)日：1999-01-26
申请号：US775770
申请日：1996-12-31
申请人： Siamak Tavallaei , Louis R. Gagliardi , Joseph Peter Miller
发明人： Siamak Tavallaei , Louis R. Gagliardi , Joseph Peter Miller
IPC分类号： G06F11/00 , G06F11/20
CPC分类号： G06F11/2017 , G06F11/0745 , G06F11/0751
摘要： A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.

19. 发明申请

US20110200059A1 BIT Inversion For Communication Interface 审中-公开
标题翻译：通讯接口的BIT反转
公开(公告)号：US20110200059A1
公开(公告)日：2011-08-18
申请号：US13126032
申请日：2008-10-30
申请人： Siamak Tavallaei
发明人： Siamak Tavallaei
IPC分类号： H04L12/56
CPC分类号： H04L25/49 , G11C7/1006
摘要： In accordance with embodiments, a system includes a first component and a second component. The system also includes a communication interface between the first and second components. A communication packet transmitted from the first component to the second component comprises a bit inversion identifier.
摘要翻译：根据实施例，系统包括第一部件和第二部件。该系统还包括第一和第二组件之间的通信接口。从第一分量发送到第二分量的通信分组包括位反转标识符。

20. 发明授权

US06608564B2 Removable memory cartridge system for use with a server or other processor-based device 有权
公开(公告)号：US06608564B2
公开(公告)日：2003-08-19
申请号：US09770100
申请日：2001-01-25
申请人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
发明人： Christian H. Post , George D. Megason , Brett D. Roscoe , Paul Santeler , John M. MacLaren , John E. Larson , Jeffery Galloway , Siamak Tavallaei , Tim W. Majni , Robert Allan Lester , Anisha Anand , Eric Rose
IPC分类号： G08B2300
CPC分类号： G06F13/4081 , G06F13/409
摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

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