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11. 发明申请

US20110278599A1 SILICON CARBIDE SEMICONDUCTOR DEVICE 有权
标题翻译：硅碳化硅半导体器件
公开(公告)号：US20110278599A1
公开(公告)日：2011-11-17
申请号：US13146812
申请日：2010-02-23
申请人： Yukiyasu Nakao , Masayuki Imaizumi , Shuhei Nakata , Naruhisa Miura
发明人： Yukiyasu Nakao , Masayuki Imaizumi , Shuhei Nakata , Naruhisa Miura
IPC分类号： H01L29/161
CPC分类号： H01L29/1608 , H01L21/0465 , H01L29/0615 , H01L29/0657 , H01L29/0696 , H01L29/1095 , H01L29/42372 , H01L29/45 , H01L29/66068 , H01L29/7396 , H01L29/7811 , H01L29/7816
摘要： A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
摘要翻译：一种能够提高开关速度而不破坏栅极绝缘膜的SiC半导体器件。此外，在由SiC构成的n型半导体基板的SiC-MOSFET中，p型半导体层全部或部分设置在p型阱层的上表面上，该p型阱层的横面为最大面积在设置在n型漂移层中的多个p型阱层之中，并且布置在栅电极焊盘正下方的最外周。 p型半导体层中含有的杂质的浓度优选大于p型阱层的浓度。

12. 发明授权

US08723259B2 Silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件
公开(公告)号：US08723259B2
公开(公告)日：2014-05-13
申请号：US13146812
申请日：2010-02-23
申请人： Yukiyasu Nakao , Masayuki Imaizumi , Shuhei Nakata , Naruhisa Miura
发明人： Yukiyasu Nakao , Masayuki Imaizumi , Shuhei Nakata , Naruhisa Miura
IPC分类号： H01L29/66
CPC分类号： H01L29/1608 , H01L21/0465 , H01L29/0615 , H01L29/0657 , H01L29/0696 , H01L29/1095 , H01L29/42372 , H01L29/45 , H01L29/66068 , H01L29/7396 , H01L29/7811 , H01L29/7816
摘要： A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.
摘要翻译：一种能够提高开关速度而不破坏栅极绝缘膜的SiC半导体器件。此外，在由SiC构成的n型半导体基板的SiC-MOSFET中，p型半导体层全部或部分设置在p型阱层的上表面上，该p型阱层的横面为最大面积在设置在n型漂移层中的多个p型阱层之中，并且布置在栅电极焊盘正下方的最外周。 p型半导体层中含有的杂质的浓度优选大于p型阱层的浓度。

13. 发明申请

US20130020586A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130020586A1
公开(公告)日：2013-01-24
申请号：US13638970
申请日：2011-04-07
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Hiroshi Watanabe
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Hiroshi Watanabe
IPC分类号： H01L29/78
CPC分类号： H01L29/1608 , H01L29/0615 , H01L29/0878 , H01L29/1095 , H01L29/1602 , H01L29/2003 , H01L29/66045 , H01L29/66068 , H01L29/66712 , H01L29/781 , H01L29/7811
摘要： A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.
摘要翻译：具有低反馈电容和低开关损耗的半导体器件。半导体器件包括：衬底; 形成在所述半导体衬底的表面上的漂移层; 多个第一阱区，形成在所述漂移层的表面上; 源区域，其是形成在每个第一阱区域的表面上的区域，并且限定插入在该区域和漂移层之间的每个第一阱区域的沟道区域; 形成在所述沟道区域上的栅电极和穿过栅极绝缘膜的所述漂移层; 以及埋在栅电极下方的漂移层内的第二阱区，并形成为分别连接到彼此相邻的每个第一阱区。

14. 发明授权

US09105715B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09105715B2
公开(公告)日：2015-08-11
申请号：US13146654
申请日：2009-04-30
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
IPC分类号： H01L29/66 , H01L29/78 , H01L29/10 , H01L29/06 , H01L29/16 , H01L29/423 , H01L29/45 , H01L29/49
CPC分类号： H01L29/7811 , H01L23/53209 , H01L29/0611 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/4238 , H01L29/45 , H01L29/4916 , H01L29/4941 , H01L29/4975 , H01L29/66068 , H01L29/7805 , H01L2924/0002 , H01L2924/00
摘要： In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.
摘要翻译：在第一导电类型的半导体衬底的第一主表面的单元区域中，第二导电类型的第一阱位于上表面。第一导电类型的扩散区位于第一阱的上表面。第一栅极绝缘膜在第一阱上，第一栅极电极在第一栅极绝缘膜上。第二导电类型的第二阱在电池区域的周边部分的第一主表面的上表面中。第二栅绝缘膜在第二阱上，厚场氧化膜位于比第二栅极绝缘膜更外侧。第二栅电极顺序地在第二栅极绝缘膜和场氧化物膜上电连接到第一栅电极。第一电极连接到第一，第二阱和扩散区。第二电极连接在半导体衬底的第二主表面上。栅极布线在场氧化膜上，绕电池区的周围，并电连接到第二栅电极。栅极布线是第二栅电极的构成物质的硅化物。

15. 发明申请

US20110284874A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110284874A1
公开(公告)日：2011-11-24
申请号：US13146654
申请日：2009-04-30
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Naoki Yutani
IPC分类号： H01L29/78 , H01L21/8238
CPC分类号： H01L29/7811 , H01L23/53209 , H01L29/0611 , H01L29/0615 , H01L29/0638 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/42372 , H01L29/4238 , H01L29/45 , H01L29/4916 , H01L29/4941 , H01L29/4975 , H01L29/66068 , H01L29/7805 , H01L2924/0002 , H01L2924/00
摘要： In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side than the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first, second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate. A gate wiring is on the field oxide film, going around a periphery of the cell region, and electrically connected to the second gate electrode. The gate wiring is a silicide of a constituting substance of the second gate electrode.
摘要翻译：在第一导电类型的半导体衬底的第一主表面的单元区域中，第二导电类型的第一阱位于上表面。第一导电类型的扩散区位于第一阱的上表面。第一栅极绝缘膜在第一阱上，第一栅极电极在第一栅极绝缘膜上。第二导电类型的第二阱在电池区域的周边部分的第一主表面的上表面中。第二栅绝缘膜在第二阱上，厚场氧化膜位于比第二栅极绝缘膜更外侧。第二栅电极顺序地在第二栅极绝缘膜和场氧化物膜上电连接到第一栅电极。第一电极连接到第一，第二阱和扩散区。第二电极连接在半导体衬底的第二主表面上。栅极布线位于场氧化膜上，绕着单元区域的周边，并与第二栅电极电连接。栅极布线是第二栅电极的构成物质的硅化物。

16. 发明授权

US08860039B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08860039B2
公开(公告)日：2014-10-14
申请号：US13638970
申请日：2011-04-07
申请人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Hiroshi Watanabe
发明人： Naruhisa Miura , Shuhei Nakata , Kenichi Ohtsuka , Shoyu Watanabe , Hiroshi Watanabe
IPC分类号： H01L29/78 , H01L29/66 , H01L29/10 , H01L29/20 , H01L29/16 , H01L29/06 , H01L29/08
CPC分类号： H01L29/1608 , H01L29/0615 , H01L29/0878 , H01L29/1095 , H01L29/1602 , H01L29/2003 , H01L29/66045 , H01L29/66068 , H01L29/66712 , H01L29/781 , H01L29/7811
摘要： A semiconductor device having a low feedback capacitance and a low switching loss. The semiconductor device includes: a substrate; a drift layer formed on a surface of the semiconductor substrate; a plurality of first well regions formed on a surface of the drift layer; a source region which is an area formed on a surface of each of the first well regions and defining, as a channel region, the surface of each of the first well regions interposed between the area and the drift layer; a gate electrode formed over the channel region and the drift layer thereacross through a gate insulating film; and second well regions buried inside the drift layer below the gate electrode and formed to be individually connected to each of the first well regions adjacent to one another.
摘要翻译：具有低反馈电容和低开关损耗的半导体器件。半导体器件包括：衬底; 形成在所述半导体衬底的表面上的漂移层; 多个第一阱区，形成在所述漂移层的表面上; 源区域，其是形成在每个第一阱区域的表面上的区域，并且限定插入在该区域和漂移层之间的每个第一阱区域的沟道区域; 形成在所述沟道区域上的栅电极和穿过栅极绝缘膜的所述漂移层; 以及埋在栅电极下方的漂移层内的第二阱区，并形成为分别连接到彼此相邻的每个第一阱区。

17. 发明申请

US20140299891A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140299891A1
公开(公告)日：2014-10-09
申请号：US14355737
申请日：2012-09-24
申请人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Tomokatsu Watanabe , Kenichi Ohtsuka , Hiroshi Watanabe , Yuji Ebiike
发明人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Tomokatsu Watanabe , Kenichi Ohtsuka , Hiroshi Watanabe , Yuji Ebiike
IPC分类号： H01L29/06 , H01L29/10 , H01L29/16
CPC分类号： H01L29/0619 , H01L29/0688 , H01L29/0692 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7396 , H01L29/7802 , H01L29/808
摘要： A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction.
摘要翻译：一种半导体器件，其可以在抑制导通损耗的增加或开关损耗的同时提高可靠性。在半导体装置中，当在半导体基板的主表面上的二维形状是单位电池时，形状是周期性地设置在漂移层的表面层中的多个阱区域的重复单元，一个单元电池并且在x轴方向上相邻的另一个单元单元在y轴方向上不对准地设置，并且在y轴方向上相邻的一个单位单元和另一个单位单元在x轴方向上不对准地设置。

18. 发明授权

US09190468B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09190468B2
公开(公告)日：2015-11-17
申请号：US14355737
申请日：2012-09-24
申请人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Tomokatsu Watanabe , Kenichi Ohtsuka , Hiroshi Watanabe , Yuji Ebiike
发明人： Shiro Hino , Naruhisa Miura , Akihiko Furukawa , Tomokatsu Watanabe , Kenichi Ohtsuka , Hiroshi Watanabe , Yuji Ebiike
IPC分类号： H01L27/118 , H01L21/44 , H01L29/06 , H01L29/739 , H01L29/66 , H01L29/78 , H01L29/16 , H01L29/10 , H01L29/808
CPC分类号： H01L29/0619 , H01L29/0688 , H01L29/0692 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/7396 , H01L29/7802 , H01L29/808
摘要： A semiconductor device that can improve reliability while suppressing increase of a conduction loss or a switching loss. In the semiconductor device, when a two-dimensional shape on a main surface of the semiconductor substrate is an unit cell, the shape being a repeating unit of a plurality of well regions periodically disposed in a surface layer of a drift layer, one unit cell and another unit cell adjacent in an x-axis direction are disposed misaligned in a y-axis direction, and one unit cell and another unit cell adjacent in the y-axis direction are disposed misaligned in the x-axis direction.
摘要翻译：一种半导体器件，其可以在抑制导通损耗的增加或开关损耗的同时提高可靠性。在半导体装置中，当在半导体基板的主表面上的二维形状是单位电池时，形状是周期性地设置在漂移层的表面层中的多个阱区域的重复单元，一个单元电池并且在x轴方向上相邻的另一个单元单元在y轴方向上不对准地设置，并且在y轴方向上相邻的一个单位单元和另一个单位单元在x轴方向上不对准地设置。

19. 发明授权

US08513735B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US08513735B2
公开(公告)日：2013-08-20
申请号：US13127564
申请日：2009-06-30
申请人： Shuhei Nakata , Shoyu Watanabe , Kenichi Otsuka , Naruhisa Miura
发明人： Shuhei Nakata , Shoyu Watanabe , Kenichi Otsuka , Naruhisa Miura
IPC分类号： H01L29/78
CPC分类号： H01L29/66068 , H01L29/41758 , H01L29/7827
摘要： A structure of a power semiconductor device, in which a P-well region having a large area and a gate electrode are opposed to each other through a field oxide film having a larger thickness than that of a gate insulating film such that the P-well region having a large area and the gate electrode are not opposed to each other through the gate insulating film, or the gate electrode is not provided above the gate insulating film that includes the P-well region having a large area therebelow.
摘要翻译：具有大面积的P阱区和栅电极的功率半导体器件的结构通过具有比栅绝缘膜的厚度大的场氧化膜彼此相对，使得P阱具有大面积的栅极绝缘膜和栅电极不通过栅极绝缘膜彼此相对，或者栅电极不设置在包括具有大面积的P阱区的栅极绝缘膜的上方。

20. 发明申请

US20120061688A1 POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件及其制造功率半导体器件的方法
公开(公告)号：US20120061688A1
公开(公告)日：2012-03-15
申请号：US13319742
申请日：2009-07-15
申请人： Shoyu Watanabe , Shuhei Nakata , Naruhisa Miura
发明人： Shoyu Watanabe , Shuhei Nakata , Naruhisa Miura
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/1095 , H01L29/1608 , H01L29/66068
摘要： In a power semiconductor device that switches at a high speed, a displacement current flows at a time of switching, so that a high voltage occurs which may cause breakdown of a thin insulating film such as a gate insulating film. A semiconductor device includes: a semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type formed on a first main surface of the semiconductor substrate; a first well region of a second conductivity type formed in a part of a surface layer of the drift layer; a second well region of the second conductivity type formed in a part of the surface layer of the drift layer at a distance from the first well region, the second well region having a smaller area than that of the first well region when seen above an upper surface thereof; a low-resistance region of the first conductivity type formed in a surface layer of the first well region, the low-resistance region having a higher impurity concentration than that of the first well region; a gate insulating film formed on and in contact with a surface of the first well region; and a gate electrode formed on and in contact with a surface of the gate insulating film.
摘要翻译：在高速切换的功率半导体器件中，位移电流在切换时流动，从而产生可能导致诸如栅极绝缘膜的薄绝缘膜破坏的高电压。半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底的第一主表面上的所述第一导电类型的漂移层; 形成在漂移层的表面层的一部分中的第二导电类型的第一阱区; 第二导电类型的第二阱区形成在距第一阱区一定距离的漂移层的表面层的一部分中，第二阱区的面积比第一阱区的面积小，当在上部表面形成在所述第一阱区的表面层中的所述第一导电类型的低电阻区域，所述低电阻区域的杂质浓度高于所述第一阱区域的杂质浓度; 形成在第一阱区的表面上并与其接触的栅极绝缘膜; 以及形成在栅极绝缘膜的表面上并与栅极绝缘膜的表面接触的栅电极。

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