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11. 发明授权

US08660125B2 Node device, integrated circuit and control method in ring transmission system 有权
标题翻译：环形传输系统中的节点设备，集成电路和控制方法
公开(公告)号：US08660125B2
公开(公告)日：2014-02-25
申请号：US13386756
申请日：2011-05-24
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： H04L12/56 , H04L12/427
CPC分类号： H04L12/437 , H04L12/40013
摘要： A node device in a ring transmission system in which a plurality of node devices are connected as a ring via serial links has a PHY transitioning between a normal mode and a loopback mode with timing that maintains symbol lock between an idle frame transmitted to a later serial link in the normal mode according a transmission instruction, and an idle frame from an earlier node device looped back for output to a later serial link during the loopback mode, thus performing relay processing on non-locally addressed data packets during the loopback mode.
摘要翻译：通过串行链路将多个节点设备作为环路连接的环形传输系统中的节点设备具有正常模式和环回模式之间的PHY转换，其中定时保持发送到后续串行的空闲帧之间的符号锁定在回送模式期间，根据传输指令以及来自较早节点设备的空闲帧循环输出到稍后的串行链路，从而在环回模式期间对非本地寻址的数据分组执行中继处理。

12. 发明授权

US08576704B2 Communication system, communication device, integrated circuit, and communication method 有权
标题翻译：通信系统，通信设备，集成电路和通信方式
公开(公告)号：US08576704B2
公开(公告)日：2013-11-05
申请号：US13059263
申请日：2010-03-17
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： G01R31/08
CPC分类号： H04L12/42 , H04L12/12 , Y02D50/20 , Y02D50/40
摘要： A communication system includes communication devices that are connected with one another in a ring via a serial link. In the communication system, one communication device issues a standby packet for causing each communication device connected to a part of the link that is not involved with data transfer to switch to standby mode. Each communication device connected to this part of the link relays the standby packet from an immediately preceding communication device in the link to an immediately succeeding communication device in the link, and after relaying the standby packet, causes the own device to switch to standby mode. Further, a communication device that performs communication with said one communication device issues a loopback packet for causing each communication device connected to a part of the link that is involved with data transfer to switch to loopback mode. Each communication device connected to this part of the link relays the loopback packet from an immediately preceding communication device in the link to an immediately succeeding communication device in the link, and after relaying the loopback packet, causes the own device to switch to loopback mode.
摘要翻译：通信系统包括通过串行链路在环中彼此连接的通信设备。在通信系统中，一个通信设备发出备用分组，使得连接到不涉及数据传输的链路的一部分的每个通信设备切换到待机模式。连接到链路的这一部分的每个通信设备将链路中的紧接在前的通信设备的备用分组中继到链路中紧接着的通信设备，并且在中继备用分组之后，使得自己的设备切换到待机模式。此外，与所述一个通信设备进行通信的通信设备发出环回分组，使得连接到涉及数据传输的链路的一部分的每个通信设备切换到环回模式。与链路的这一部分连接的每个通信装置将链路中的紧急通信装置的环回分组中继到链路中的紧随其后的通信装置，并且在中继环回分组之后，使得本装置切换到环回模式。

13. 发明申请

US20110276748A1 NON-VOLATILE STORAGE DEVICE, HOST DEVICE, STORAGE SYSTEM, DATA COMMUNICATION METHOD AND PROGRAM 有权
标题翻译：非易失存储设备，主机设备，存储系统，数据通信方法和程序
公开(公告)号：US20110276748A1
公开(公告)日：2011-11-10
申请号：US13144594
申请日：2010-12-01
申请人： Masayuki Toyama , Tadashi Ono , Shinichiro Nishioka
发明人： Masayuki Toyama , Tadashi Ono , Shinichiro Nishioka
IPC分类号： G06F12/02
CPC分类号： G06F9/4403
摘要： In a memory system including a host device and one or more nonvolatile memory devices, the host device reads, from a nonvolatile memory device connected in the system, a boot code used to operate a CPU of the host device before the CPU is activated. The boot code reading process is required to be performed with a simple method. A host device (2) transmits a first symbol including a synchronous code to a nonvolatile memory device (1). The nonvolatile memory device (1) receives the first symbol from the host device (2), and transmits a first symbol that is identical to the received first symbol to the host device (2), and then transmits a boot code to the host device (2). In this manner, the host device (2) reads a boot code from the nonvolatile memory device 1 with a simple method.
摘要翻译：在包括主机设备和一个或多个非易失性存储设备的存储器系统中，主机设备从连接在系统中的非易失性存储设备中读取用于在CPU被激活之前操作主机设备的CPU的引导代码。引导代码读取过程需要以简单的方法执行。主机设备（2）将包括同步码的第一符号发送到非易失性存储设备（1）。非易失性存储器件（1）从主机（2）接收第一符号，并将与接收到的第一符号相同的第一符号发送到主机（2），然后将引导代码发送到主机（2）。以这种方式，主机设备（2）以简单的方法从非易失性存储设备1读取引导代码。

14. 发明申请

US20100023736A1 RECONFIGURABLE CIRCUIT, RESET METHOD, AND CONFIGURATION INFORMATION GENERATION DEVICE 审中-公开
标题翻译：可重构电路，复位方法和配置信息生成装置
公开(公告)号：US20100023736A1
公开(公告)日：2010-01-28
申请号：US12520909
申请日：2008-10-30
申请人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
发明人： Takashi Morimoto , Shinichiro Nishioka , Koji Asai
IPC分类号： G06F9/00 , G06F9/30 , G06F9/45
CPC分类号： H03K19/17772 , G06F1/24 , H03K19/17756 , H03K19/1776
摘要： The present invention provides a reconfigurable circuit that comprises a plurality of reconfiguration cells and changes a configuration of a computation processing unit included in each of the reconfiguration cells. Here, each of the reconfiguration cells further includes: a computation storage unit operable to store a result of a computation performed by the computation processing unit; a flag holding unit operable to hold an initialization flag indicating whether an initialization of the computation storage unit is required; and an initialization control unit operable to, during the configuration change of the computation processing unit, control the initialization of the computation storage unit based on the initialization flag held by the flag holding unit.
摘要翻译：本发明提供一种可重构电路，其包括多个重新配置单元，并且改变每个重新配置单元中包括的计算处理单元的配置。这里，每个重新配置单元还包括：计算存储单元，用于存储由计算处理单元执行的计算结果; 标记保持单元，用于保持指示是否需要计算存储单元的初始化的初始化标志; 以及初始化控制单元，其可操作以在所述计算处理单元的配置改变期间，基于由所述标志保持单元保持的初始化标志来控制所述计算存储单元的初始化。

15. 发明授权

US09379974B2 Transfer control device, integrated circuit thereof, transfer control method, and transfer control system 有权
标题翻译：转移控制装置，集成电路，转移控制方法和转移控制系统
公开(公告)号：US09379974B2
公开(公告)日：2016-06-28
申请号：US13984928
申请日：2012-01-27
申请人： Yuusaku Ohta , Shinichiro Nishioka
发明人： Yuusaku Ohta , Shinichiro Nishioka
IPC分类号： H04L12/741 , H04L12/46 , H04L12/64 , H04L29/12
CPC分类号： H04L45/74 , H04L12/4625 , H04L12/6418 , H04L61/2038
摘要： To achieve efficient data transfer between a first network and a second network, and, in particular, to reduce processing load pertaining to address conversion, a transfer control device in the first network acquires an address of a transfer target device in the second network, and assigns the acquired address to a transfer device in the first network. When data transmitted through the first network is to be transferred to the transfer target device via the transfer device, there is no need to perform address conversion as the transfer device and the transfer target device are assigned the same address.
摘要翻译：为了实现第一网络和第二网络之间的有效数据传输，并且特别地，为了减少与地址转换相关的处理负担，第一网络中的传输控制设备获取第二网络中的传送目标设备的地址，以及将所获取的地址分配给第一网络中的传送设备。当通过第一网络发送的数据将经由传送装置传送到转移目标装置时，不需要执行地址转换作为传送装置，并且传送目标装置被分配相同的地址。

16. 发明授权

US08464020B2 Non-volatile storage device, host device, storage system, data communication method and program 有权
标题翻译：非易失性存储设备，主机设备，存储系统，数据通信方式和程序
公开(公告)号：US08464020B2
公开(公告)日：2013-06-11
申请号：US13144594
申请日：2010-12-01
申请人： Masayuki Toyama , Tadashi Ono , Shinichiro Nishioka
发明人： Masayuki Toyama , Tadashi Ono , Shinichiro Nishioka
IPC分类号： G06F13/00
CPC分类号： G06F9/4403
摘要： In a memory system including a host device and one or more nonvolatile memory devices, the host device reads, from a nonvolatile memory device connected in the system, a boot code used to operate a CPU of the host device before the CPU is activated. The boot code reading process is required to be performed with a simple method. A host device (2) transmits a first symbol including a synchronous code to a nonvolatile memory device (1). The nonvolatile memory device (1) receives the first symbol from the host device (2), and transmits a first symbol that is identical to the received first symbol to the host device (2), and then transmits a boot code to the host device (2). In this manner, the host device (2) reads a boot code from the nonvolatile memory device 1 with a simple method.
摘要翻译：在包括主机设备和一个或多个非易失性存储设备的存储器系统中，主机设备从连接在系统中的非易失性存储设备中读取用于在CPU被激活之前操作主机设备的CPU的引导代码。引导代码读取过程需要以简单的方法执行。主机设备（2）将包括同步码的第一符号发送到非易失性存储设备（1）。非易失性存储器件（1）从主机（2）接收第一符号，并将与接收到的第一符号相同的第一符号发送到主机（2），然后将引导代码发送到主机（2）。以这种方式，主机设备（2）以简单的方法从非易失性存储设备1读取引导代码。

17. 发明授权

US07863930B2 Programmable device, control method of device and information processing system 有权
标题翻译：可编程器件，器件和信息处理系统的控制方法
公开(公告)号：US07863930B2
公开(公告)日：2011-01-04
申请号：US12598099
申请日：2008-09-18
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： G06F7/38 , H03K19/177 , H01L25/00
CPC分类号： H03K19/17772 , H03K19/17784
摘要： A programmable device operates at high speed while reducing power consumption. The programmable device includes a plurality of processing tiles each including a configuration memory and a core logic unit, a configuration control unit for programming them, and a power control unit for cutting off a power supply depending on an operating state. The power supply of the core logic unit is cut off after saving the internal state of the core logic unit in the configuration memory, and power is supplied again to the core logic unit before the internal state is restored from the configuration memory to the core logic unit, thus saving power while maintaining the internal state.
摘要翻译：可编程器件以高速度工作，同时降低功耗。可编程装置包括多个处理瓦片，每个处理瓦片包括配置存储器和核心逻辑单元，用于对它们进行编程的配置控制单元，以及根据操作状态切断电源的电源控制单元。在将核心逻辑单元的内部状态保存在配置存储器中之后，核心逻辑单元的电源被切断，并且在将内部状态从配置存储器恢复到核心逻辑之前再次提供给核心逻辑单元的电力单位，从而节省电力，同时保持内部状态。

18. 发明申请

US20060005056A1 Multiprocessor control apparatus, control method thereof, and integrated circuit 有权
标题翻译：多处理器控制装置，其控制方法和集成电路
公开(公告)号：US20060005056A1
公开(公告)日：2006-01-05
申请号：US11169026
申请日：2005-06-27
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3228
摘要： Provided is a multiprocessor control apparatus that restrains impairment of processing speed of entire operations, while pursuing power consumption saving for a multiprocessor. The multiprocessor control apparatus has: an execution control unit operable to control a processor to, when processors other than the processor have ended respective operations performed in parallel, start performing an operation that uses a result of the operations; and a power control unit operable to control power supply to the processor, where when the processor has been under power-supply restriction, the power control unit cancels the power-supply restriction before one of the other processors, which is the last of all the other processors to end a corresponding operation, ends the corresponding operation.
摘要翻译：提供了一种多处理器控制装置，其抑制整个操作的处理速度的损害，同时为多处理器寻求功耗节省。多处理器控制装置具有：执行控制单元，用于控制处理器，当处理器之外的处理器已经结束并行执行的各个操作时，开始执行使用操作结果的操作; 以及功率控制单元，其可操作以控制对所述处理器的电力供应，其中当所述处理器处于电源限制状态时，所述功率控制单元在所有其他处理器中的最后一个处理器之前取消所述电源限制其他处理器结束相应的操作，结束相应的操作。

19. 发明授权

US09832279B2 Station, target apparatus, initiator apparatus, communication system, and communication method 有权
公开(公告)号：US09832279B2
公开(公告)日：2017-11-28
申请号：US13985999
申请日：2012-03-09
申请人： Shinichiro Nishioka , Yuusaku Ohta , Kozo Nishimura
发明人： Shinichiro Nishioka , Yuusaku Ohta , Kozo Nishimura
IPC分类号： G06F15/16 , H04L29/08 , H04L12/24 , H04N21/6371
CPC分类号： H04L67/288 , H04L41/0846 , H04L41/0853 , H04L67/2842 , H04N21/6371
摘要： A plurality of networks each having a host are connected to achieve a transparent transaction between devices belonging to the different networks. A target apparatus includes a station and a host. In response to a get device handle request from an initiator apparatus, the station acquires, from the host, configuration information of a target device and relays transactions between the initiator apparatus and the target device, without requiring involvement of the host.

20. 发明授权

US08903000B2 Transmission circuit, reception circuit, transmission method, reception method, communication system and communication method therefor 有权
标题翻译：传输电路，接收电路，传输方法，接收方法，通信系统及其通信方法
公开(公告)号：US08903000B2
公开(公告)日：2014-12-02
申请号：US13823575
申请日：2011-09-30
申请人： Shinichiro Nishioka
发明人： Shinichiro Nishioka
IPC分类号： H04B1/52
CPC分类号： H04L7/10 , H04L1/0057 , H04L1/0083 , H04L25/4908 , H04W56/00
摘要： In transmission of channel-coded serial data, early establishment of symbol synchronization between a transmitter and a receiver is achieved while reducing coding loss in transmission of valid data. In an idle period for not transmitting the valid data, a transmitting circuit selects first channel coding (e.g. 8B/10B coding) enabling early establishment of synchronization and transmits a synchronization symbol encoded using the first channel coding. In response to this, a receiving circuit establishes and maintains symbol synchronization. When the valid data is transmitted, the transmitting circuit transmits a symbol indicating a packet start position, selects second channel coding (e.g. 64B/66B coding) having less coding loss than the first channel coding, and transmits the valid data encoded using the second channel coding. Upon reception of the symbol indicating the packet start position, the receiving circuit switches to reception using the second channel coding and receives the valid data.
摘要翻译：在传输信道编码的串行数据时，实现了发射机和接收机之间的符号同步的早期建立，同时减少了传输有效数据时的编码丢失。在不发送有效数据的空闲时段中，发送电路选择能够提前建立同步的第一信道编码（例如8B / 10B编码），并发送使用第一信道编码编码的同步符号。响应于此，接收电路建立并维持符号同步。当发送有效数据时，发送电路发送表示分组开始位置的符号，选择比第一信道编码更少的编码丢失的第二信道编码（例如64B / 66B编码），并发送使用第二信道编码的有效数据编码。在接收到指示分组开始位置的符号时，接收电路使用第二信道编码切换到接收，并接收有效数据。

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