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11. 发明授权

US06292881B1 Microprocessor, operation process execution method and recording medium 有权
标题翻译：微处理器，操作过程执行方法和记录介质
公开(公告)号：US06292881B1
公开(公告)日：2001-09-18
申请号：US09257198
申请日：1999-02-25
申请人： Ritsuko Tanaka , Yuji Nomura , Toru Tsuruta , Nobuyuki Iwasaki
发明人： Ritsuko Tanaka , Yuji Nomura , Toru Tsuruta , Nobuyuki Iwasaki
IPC分类号： G06F940
CPC分类号： G06F9/3017 , G06F9/30145
摘要： A microprocessor capable of executing a process instruction having at least one RISC type instruction is constructed to include an instruction decoding section for decoding a microcode including information which indicates transfer contents of input and output data and address information which indicates a storage location of the process instruction, a data reading section for reading input data corresponding to the information which indicates the transfer contents of the input and output data decoded by the instruction decoding section and reading the process instruction corresponding to the address information, and an operation process executing section for implementing one or a plurality of operation unit resources capable of executing an operation process according to the input data read by the data reading section and the process instruction.
摘要翻译：能够执行具有至少一个RISC型指令的处理指令的微处理器被构造成包括用于解码包括指示输入和输出数据的传送内容的信息的微码的指令解码部分和指示处理指令的存储位置的地址信息数据读取部分，用于读取对应于指示由指令解码部分解码的输入和输出数据的传送内容并且读取对应于地址信息的处理指令的信息的输入数据;以及操作处理执行部分，用于实现一个或能够根据由数据读取部读取的输入数据和处理指令执行动作处理的多个操作部资源。

12. 发明授权

US08253820B2 Image processing apparatus and image processing method 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US08253820B2
公开(公告)日：2012-08-28
申请号：US12813880
申请日：2010-06-11
申请人： Masayoshi Shimizu , Toru Tsuruta , Yuushi Toyoda
发明人： Masayoshi Shimizu , Toru Tsuruta , Yuushi Toyoda
IPC分类号： H04N5/235
CPC分类号： H04N5/20 , G06T5/009 , G06T5/40 , G06T2207/10016
摘要： An image processing apparatus includes a low-frequency-component storage unit that stores therein a low-frequency component generated from a frame in an input moving image composed of a plurality of frames, a low-frequency-component generating unit that generates a low-frequency component from an N-th frame of the input moving image, and stores the low-frequency component in the low-frequency-component storage unit, and a dynamic-range correcting unit that corrects a dynamic range by using an (N+1)-th or later frame of the input moving image and the low-frequency component of the N-th frame stored in the low-frequency-component storage unit.
摘要翻译：一种图像处理装置，包括：低频分量存储单元，其存储由多个帧构成的输入运动图像中的从帧生成的低频分量;低频分量生成单元，并且将低频分量存储在低频分量存储单元中，以及动态范围校正单元，其通过使用第（N + 1）个频率分量来校正动态范围以及存储在低频分量存储单元中的第N帧的低频分量。

13. 发明申请

US20070033369A1 Reconfigurable integrated circuit device 审中-公开
标题翻译：可重构集成电路器件
公开(公告)号：US20070033369A1
公开(公告)日：2007-02-08
申请号：US11340871
申请日：2006-01-27
申请人： Ichiro Kasama , Toru Tsuruta , Masaru Nishida
发明人： Ichiro Kasama , Toru Tsuruta , Masaru Nishida
IPC分类号： G06F12/00
CPC分类号： G06F15/8007
摘要： A reconfigurable integrated circuit device which is dynamically constructed to be an arbitrary operation status based on a configuration data, has a plurality of clusters including operation processor elements, a memory processor element, and an inter-processor element switch group for connecting the elements in an arbitrary status; an inter-cluster switch group for constructing data paths between the clusters in an arbitrary status; and an external memory bus. A direct memory access control section, for executing the data transfer between the memory processor element and the external memory by direct memory access responding to an access request from the memory processor elements of the plurality of clusters, is further provided.
摘要翻译：动态构造为基于配置数据的任意操作状态的可重构集成电路装置具有包括操作处理器元件，存储器处理器元件和处理器间元件开关组的多个集群，用于将元件任意状态; 用于在任意状态下构建簇之间的数据路径的群集间切换组; 和外部存储器总线。一种直接存储器访问控制部分，用于通过响应来自多个集群的存储器处理器元件的访问请求的直接存储器访问来执行存储处理器元件和外部存储器之间的数据传输。

14. 发明申请

US20050223136A1 System and method for controlling DMA data transfer 失效
标题翻译：用于控制DMA数据传输的系统和方法
公开(公告)号：US20050223136A1
公开(公告)日：2005-10-06
申请号：US11140732
申请日：2005-06-01
申请人： Ryuta Tanaka , Toru Tsuruta , Ritsuko Tanaka , Norichika Kumamoto
发明人： Ryuta Tanaka , Toru Tsuruta , Ritsuko Tanaka , Norichika Kumamoto
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored in the DMAC memory. Each time a new DMA request is received, the DMAC saves its parameters in a DMA request parameter table, and each DMA request parameter table is registered with a DMA request management table. In this way, the received DMA requests are queued in the DMA request management table. They are executed in a first-in first-out fashion. The progress of ongoing DMA transfers are managed in a DMA channel status table disposed for each DMA channel.
摘要翻译：一种数据传输控制系统，可以改变DMA传输的方式以满足每个应用的要求。数据传输控制系统包括DMA控制器（DMAC）和专用于DMA控制目的的DMAC存储器。 DMAC根据存储在DMAC存储器中的DMA程序执行DMA传输。每当接收到新的DMA请求时，DMAC将其参数保存在DMA请求参数表中，并且每个DMA请求参数表都向DMA请求管理表注册。以这种方式，接收的DMA请求在DMA请求管理表中排队。他们以先到先得的方式执行。正在进行的DMA传输的进展在针对每个DMA通道设置的DMA通道状态表中进行管理。

15. 发明申请

US20100202712A1 IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD 有权
标题翻译：图像处理装置和图像处理方法
公开(公告)号：US20100202712A1
公开(公告)日：2010-08-12
申请号：US12767376
申请日：2010-04-26
申请人： Toru Tsuruta , Masayoshi Shimizu , Yuushi Toyoda , Eishi Morimatsu
发明人： Toru Tsuruta , Masayoshi Shimizu , Yuushi Toyoda , Eishi Morimatsu
IPC分类号： G06T5/00
CPC分类号： G06T5/50 , G06T5/002 , G06T5/20 , G06T2207/10016 , G06T2207/20192 , H04N7/012
摘要： An image processing apparatus holds a plurality of intermediate smoothed images smoothed at a plurality of preset level values, reduces the N-th frame image of a moving image received from the outside to generate a reduced image, performs a smoothing process on the generated reduced image at the plurality of preset level values to generate a plurality of intermediate smoothed images, stores the generated intermediate smoothed images in an intermediate smoothed image storing unit, acquires, when generating the smoothed images of the frames after the (N+1)-th frame, one or a plurality of intermediate smoothed images from the plurality of intermediate smoothed images of the N-th frame stored in the intermediate smoothed image storing unit, synthesizes the acquired intermediate smoothed images of the N-th frame and the frames after the (N+1)-th frame of the moving image received from the outside, and generates smoothed images.
摘要翻译：图像处理装置保持以多个预设电平值平滑的多个中间平滑图像，减少从外部接收的运动图像的第N帧图像以生成缩小图像，对所生成的缩小图像执行平滑处理在多个预设电平值上生成多个中间平滑图像，将生成的中间平滑图像存储在中间平滑图像存储单元中，在第（N + 1）帧之后生成帧的平滑图像时获取，从中间平滑图像存储单元中存储的第N帧的多个中间平滑图像中的一个或多个中间平滑图像合成所获取的第N帧的中间平滑图像和（N +1）帧，并且产生平滑图像。

16. 发明授权

US07415550B2 System and method for controlling DMA data transfer 失效
标题翻译：用于控制DMA数据传输的系统和方法
公开(公告)号：US07415550B2
公开(公告)日：2008-08-19
申请号：US11140732
申请日：2005-06-01
申请人： Ryuta Tanaka , Toru Tsuruta , Ritsuko Tanaka , Norichika Kumamoto
发明人： Ryuta Tanaka , Toru Tsuruta , Ritsuko Tanaka , Norichika Kumamoto
IPC分类号： G06F3/00 , G06F13/28
CPC分类号： G06F13/28
摘要： A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored in the DMAC memory. Each time a new DMA request is received, the DMAC saves its parameters in a DMA request parameter table, and each DMA request parameter table is registered with a DMA request management table. In this way, the received DMA requests are queued in the DMA request management table. They are executed in a first-in first-out fashion. The progress of ongoing DMA transfers are managed in a DMA channel status table disposed for each DMA channel.
摘要翻译：一种数据传输控制系统，可以改变DMA传输的方式以满足每个应用的要求。数据传输控制系统包括DMA控制器（DMAC）和专用于DMA控制目的的DMAC存储器。 DMAC根据存储在DMAC存储器中的DMA程序执行DMA传输。每当接收到新的DMA请求时，DMAC将其参数保存在DMA请求参数表中，并且每个DMA请求参数表都向DMA请求管理表注册。以这种方式，接收的DMA请求在DMA请求管理表中排队。他们以先到先得的方式执行。正在进行的DMA传输的进展在针对每个DMA通道设置的DMA通道状态表中进行管理。

17. 发明申请

US20070174506A1 Data processing apparatus 审中-公开
标题翻译：数据处理装置
公开(公告)号：US20070174506A1
公开(公告)日：2007-07-26
申请号：US11397804
申请日：2006-04-05
申请人： Toru Tsuruta
发明人： Toru Tsuruta
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A data processing apparatus in which DMA transfer is performed. When a processor in a data processing unit outputs a first request to read data managed by a data management unit, a receiver-side DMA controller outputs a second request for DMA transfer, from the data processing unit to the data management unit through a dedicated line. Next, a memory controller in the data management unit reads out from the memory the data designated by the second request, and stores the data in a buffer. Then, a transmitter-side DMA controller acquires a right of use of a bus, and the memory controller transfers the data stored in the buffer, through the bus by DMA, and writes the data in a data storage area in the data processing unit.
摘要翻译：执行DMA传输的数据处理装置。当数据处理单元中的处理器输出读取由数据管理单元管理的数据的第一请求时，接收侧DMA控制器通过专用线从数据处理单元向数据管理单元输出DMA传送的第二请求。接下来，数据管理单元中的存储器控制器从存储器读出由第二请求指定的数据，并将数据存储在缓冲器中。然后，发送器侧DMA控制器获取总线的使用权，并且存储器控制器通过DMA通过总线传送存储在缓冲器中的数据，并将数据写入数据处理单元中的数据存储区域。

18. 发明授权

US06567909B2 Parallel processor system 失效
标题翻译：并行处理器系统
公开(公告)号：US06567909B2
公开(公告)日：2003-05-20
申请号：US09847397
申请日：2001-05-03
申请人： Toru Tsuruta , Yuji Nomura
发明人： Toru Tsuruta , Yuji Nomura
IPC分类号： G06F1516
CPC分类号： G06F15/17375 , G06F15/173 , G06F15/17337
摘要： A parallel processor system is constructed to include a pair of parallel buses (2, 3), pipeline buses (9), a plurality of processor nodes (1-1 to 1-N) having functions of carrying out an operation process in response to an instruction and transferring data, cluster switches (5-1 to 5-N, 6-1 to 6-N, 7-1a to 7-La, 7-1b to 7-+b, 8-1a to 8-Ma, 8-1b to 8-(M−1)b) having a plurality of connection modes and controlling connections of the parallel buses, the pipeline buses and the processor nodes, and a switch controller (4) controlling the connection mode of the cluster switches and coupling the processor nodes in series and/or in parallel.
摘要翻译：并行处理器系统被构造为包括一对并行总线（2,3），流水线总线（9），具有响应于以下操作的功能的多个处理器节点（1-1至1-N）指令和传送数据，簇交换机（5-1至5-N，6-1至6-N，7-1a至7-La，7-1b至7- + b，8-1a至8-Ma， 8-1b至8-（M-1）b）具有多个连接模式并控制并行总线，管线总线和处理器节点的连接以及控制集群交换机的连接模式的交换机控制器（4）并且串联和/或并联耦合处理器节点。

19. 发明授权

US06567898B1 Memory controller and an information processing apparatus with improved efficiency 失效
标题翻译：存储器控制器和提高效率的信息处理设备
公开(公告)号：US06567898B1
公开(公告)日：2003-05-20
申请号：US09609972
申请日：2000-07-06
申请人： Toru Tsuruta
发明人： Toru Tsuruta
IPC分类号： G06F1200
CPC分类号： G11C7/1063 , G11C7/1006
摘要： A memory controller includes a memory unit having an n-byte memory data width, a register unit consecutively reading out, in response to an enable signal supplied thereto, data from the memory unit having n-byte size, the register unit further recording therein the data read out from the memory unit in the form of continuous data of 2n−1 bytes including the last data read out from the memory unit, a shifter unit selecting consecutively a block of continuous n-byte data from the continuous data of 2n−1 bytes recorded in the register unit, the shifter unit supplying the continuous n-byte data block to an output terminal, and a control unit controlling the memory unit, the register unit and the shifter unit.
摘要翻译：存储器控制器包括具有n字节存储器数据宽度的存储器单元，响应于向其提供的使能信号连续读出的寄存器单元，来自具有n字节大小的存储器单元的数据，该寄存器单元进一步在其中记录从存储器单元读出的数据以包含从存储器单元读出的最后数据的2n-1个字节的连续数据的形式读出;移位器单元，从2n-1的连续数据连续地选择连续的n字节数据块记录在寄存器单元中的字节，将连续的n字节数据块提供给输出端的移位单元，以及控制存储单元，寄存器单元和移位单元的控制单元。

20. 发明授权

US06470380B1 Signal processing device accessible as memory 失效
标题翻译：信号处理设备作为存储器访问
公开(公告)号：US06470380B1
公开(公告)日：2002-10-22
申请号：US08955089
申请日：1997-10-21
申请人： Hideki Yoshizawa , Toru Tsuruta , Norichika Kumamoto , Yuji Nomura
发明人： Hideki Yoshizawa , Toru Tsuruta , Norichika Kumamoto , Yuji Nomura
IPC分类号： G06F15167
CPC分类号： G06F9/5066 , G06F9/5011 , G06F12/0813 , G06F12/1466 , G06F2209/509
摘要： A signal processing device is provided by connecting information processing units to each other using communication links and connecting the information processing units to each other and a host processor using an external bus. Parallel and pipe-line processing is accommodated by communication between the information processing units via the communication links and respective storage units of the information processing units and also by communication between the host processor and the information processing units via the external bus and the respective storage units. The host processor can communicate with the information processing units via the external bus through the respective storage units, the storage units being accessible as memory by the host processor. If each information processing unit is implemented on a single chip as an integrated circuit, the signal processing device can be incorporated in a computer in the same manner as conventional memory device are incorporated.
摘要翻译：通过使用通信链路将信息处理单元彼此连接并将信息处理单元彼此连接并使用外部总线来连接主处理器来提供信号处理设备。通过通信链路和信息处理单元的各个存储单元之间的信息处理单元之间的通信以及经由外部总线和各个存储单元的主处理器和信息处理单元之间的通信来适应并行和管线处理。主机处理器可以通过外部总线通过相应的存储单元与信息处理单元进行通信，存储单元可由主机处理器作为存储器访问。如果每个信息处理单元在作为集成电路的单个芯片上实现，则信号处理设备可以以与传统的存储器件相同的方式并入计算机中。

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