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1. 发明申请

US20080024668A1 Method, apparatus, and computer product for eliminating noise 审中-公开
标题翻译：用于消除噪音的方法，设备和计算机产品
公开(公告)号：US20080024668A1
公开(公告)日：2008-01-31
申请号：US11646858
申请日：2006-12-28
申请人： Ritsuko Tanaka , Takashi Hamano
发明人： Ritsuko Tanaka , Takashi Hamano
IPC分类号： H04N5/00
CPC分类号： H04N5/21 , H04N7/0115
摘要： A film determining unit determines whether input image data are originated from a film source. A controller determines a strength at which noise is to be eliminated from the image data based on the result of determination made by the film determining unit. A noise eliminating unit eliminates noise from the image data based on the strength determined by the controller. Specifically, when image data are originated from film-recorded images, the noise elimination strength is decreased so that film grains included in the image data are preserved.
摘要翻译：电影确定单元确定输入的图像数据是否源自电影来源。控制器基于由影像确定单元进行的确定结果，从图像数据中确定要消除噪声的强度。噪声消除单元基于由控制器确定的强度来消除图像数据中的噪声。具体地，当图像数据来自胶片记录图像时，噪声消除强度降低，从而保留包含在图像数据中的胶片颗粒。

2. 发明申请

US20050223136A1 System and method for controlling DMA data transfer 失效
标题翻译：用于控制DMA数据传输的系统和方法
公开(公告)号：US20050223136A1
公开(公告)日：2005-10-06
申请号：US11140732
申请日：2005-06-01
申请人： Ryuta Tanaka , Toru Tsuruta , Ritsuko Tanaka , Norichika Kumamoto
发明人： Ryuta Tanaka , Toru Tsuruta , Ritsuko Tanaka , Norichika Kumamoto
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored in the DMAC memory. Each time a new DMA request is received, the DMAC saves its parameters in a DMA request parameter table, and each DMA request parameter table is registered with a DMA request management table. In this way, the received DMA requests are queued in the DMA request management table. They are executed in a first-in first-out fashion. The progress of ongoing DMA transfers are managed in a DMA channel status table disposed for each DMA channel.
摘要翻译：一种数据传输控制系统，可以改变DMA传输的方式以满足每个应用的要求。数据传输控制系统包括DMA控制器（DMAC）和专用于DMA控制目的的DMAC存储器。 DMAC根据存储在DMAC存储器中的DMA程序执行DMA传输。每当接收到新的DMA请求时，DMAC将其参数保存在DMA请求参数表中，并且每个DMA请求参数表都向DMA请求管理表注册。以这种方式，接收的DMA请求在DMA请求管理表中排队。他们以先到先得的方式执行。正在进行的DMA传输的进展在针对每个DMA通道设置的DMA通道状态表中进行管理。

3. 发明授权

US07269831B2 Multiprocessor system, multiprocessor control method, and multiprocessor control program retaining computer-readable recording medium 失效
标题翻译：多处理器系统，多处理器控制方法和多处理器控制程序，保留计算机可读记录介质
公开(公告)号：US07269831B2
公开(公告)日：2007-09-11
申请号：US09987887
申请日：2001-11-16
申请人： Ryuta Tanaka , Norichika Kumamoto , Toru Tsuruta , Ritsuko Tanaka , Nobuyuki Iwasaki , Teruo Ishihara
发明人： Ryuta Tanaka , Norichika Kumamoto , Toru Tsuruta , Ritsuko Tanaka , Nobuyuki Iwasaki , Teruo Ishihara
IPC分类号： G06F9/46 , G06F15/00
CPC分类号： G06F9/4806 , G06F9/461 , Y02D10/24
摘要： The present invention relates to a multiprocessor system, which comprises two or more processor elements to be executed by a common program, a control section for switching such plural processor elements one from another for execution by the common program, and a storing section storing handover information relating to the common program which information is to be handover from the one processor element to the another processor element. This not only optimizes each of the functions of the processor elements, but also achieves certain delivery or interchange of the information between these process or elements, and even reduces the power consumption.
摘要翻译：多处理器系统技术领域本发明涉及一种多处理器系统，其包括由公共程序执行的两个或多个处理器元件，用于将这些多个处理器元件彼此之间切换以便由公共程序执行的控制部分，以及存储切换信息的存储部件涉及该信息将从一个处理器元件切换到另一个处理器元件的公共程序。这不仅优化了处理器元件的每个功能，而且还实现了这些处理器元件之间的信息的某些传送或交换，甚至降低了功耗。

4. 发明授权

US08497937B2 Converting device and converting method of video signals 失效
标题翻译：视频信号的转换装置和转换方法
公开(公告)号：US08497937B2
公开(公告)日：2013-07-30
申请号：US11787979
申请日：2007-04-18
申请人： Teruyuki Satou , Hideki Matsuoka , Ritsuko Tanaka
发明人： Teruyuki Satou , Hideki Matsuoka , Ritsuko Tanaka
IPC分类号： H04N7/01
CPC分类号： H04N7/012 , H04N5/147 , H04N7/0115 , H04N19/112 , H04N19/16 , H04N19/182 , H04N19/40 , H04N19/577
摘要： To enable a progressive synthesization process suited to each video signal even in such a case that a difference between video signals based on a video transmission sequence and the video signals not based on the video transmission sequence, is fuzzy. A converting device according to the present invention detects as to whether a result of evaluation about whether or not inputted interlaced video signals are video signals based on a video transmission sequence meets a first standard and a second standard or not, converts the interlaced video signals into progressive video signals on the basis of the video transmission sequence when detecting that the interlaced signals meet the first standard, converts the interlaced video signals into the progressive video signals on a pixel selective basis when detecting that the interlaced signals do not meet the first standard but meet the second standard, and converts the interlaced signals into the progressive video signals on a pixel interpolative basis when the interlaced signals meet neither the first standard nor the second standard.
摘要翻译：即使在基于视频传输序列的视频信号和不基于视频传输序列的视频信号之间的差异是模糊的情况下，也能适用于每个视频信号的逐行合成处理。根据本发明的转换装置检测是否基于视频传输序列输入的隔行视频信号是视频信号的评估结果是否符合第一标准和第二标准，将隔行扫描视频信号转换成当检测到隔行信号满足第一标准时，基于视频传输顺序的逐行视频信号，当检测到隔行扫描信号不满足第一标准时，以像素选择为基础将隔行扫描视频信号转换成逐行视频信号，但是满足第二标准，并且当隔行信号既不符合第一标准也不满足第二标准时，以像素插值为基础将隔行信号转换为逐行视频信号。

5. 发明授权

US07415550B2 System and method for controlling DMA data transfer 失效
标题翻译：用于控制DMA数据传输的系统和方法
公开(公告)号：US07415550B2
公开(公告)日：2008-08-19
申请号：US11140732
申请日：2005-06-01
申请人： Ryuta Tanaka , Toru Tsuruta , Ritsuko Tanaka , Norichika Kumamoto
发明人： Ryuta Tanaka , Toru Tsuruta , Ritsuko Tanaka , Norichika Kumamoto
IPC分类号： G06F3/00 , G06F13/28
CPC分类号： G06F13/28
摘要： A data transfer control system that can change the way of DMA transfers to meet the requirements of each application. The data transfer control system includes a DMA controller (DMAC) and a DMAC memory dedicated for DMA control purposes. The DMAC performs DMA transfers according to a DMA program stored in the DMAC memory. Each time a new DMA request is received, the DMAC saves its parameters in a DMA request parameter table, and each DMA request parameter table is registered with a DMA request management table. In this way, the received DMA requests are queued in the DMA request management table. They are executed in a first-in first-out fashion. The progress of ongoing DMA transfers are managed in a DMA channel status table disposed for each DMA channel.
摘要翻译：一种数据传输控制系统，可以改变DMA传输的方式以满足每个应用的要求。数据传输控制系统包括DMA控制器（DMAC）和专用于DMA控制目的的DMAC存储器。 DMAC根据存储在DMAC存储器中的DMA程序执行DMA传输。每当接收到新的DMA请求时，DMAC将其参数保存在DMA请求参数表中，并且每个DMA请求参数表都向DMA请求管理表注册。以这种方式，接收的DMA请求在DMA请求管理表中排队。他们以先到先得的方式执行。正在进行的DMA传输的进展在针对每个DMA通道设置的DMA通道状态表中进行管理。

6. 发明申请

US20070252894A1 Converting device and converting method of video signals 失效
标题翻译：视频信号的转换装置和转换方法
公开(公告)号：US20070252894A1
公开(公告)日：2007-11-01
申请号：US11787979
申请日：2007-04-18
申请人： Teruyuki Satou , Hideki Matsuoka , Ritsuko Tanaka
发明人： Teruyuki Satou , Hideki Matsuoka , Ritsuko Tanaka
IPC分类号： H04N5/253 , H04N11/20
CPC分类号： H04N7/012 , H04N5/147 , H04N7/0115 , H04N19/112 , H04N19/16 , H04N19/182 , H04N19/40 , H04N19/577
摘要： To enable a progressive synthesization process suited to each video signal even in such a case that a difference between video signals based on a video transmission sequence and the video signals not based on the video transmission sequence, is fuzzy. A converting device according to the present invention detects as to whether a result of evaluation about whether or not inputted interlaced video signals are video signals based on a video transmission sequence meets a first standard and a second standard or not, converts the interlaced video signals into progressive video signals on the basis of the video transmission sequence when detecting that the interlaced signals meet the first standard, converts the interlaced video signals into the progressive video signals on a pixel selective basis when detecting that the interlaced signals do not meet the first standard but meet the second standard, and converts the interlaced signals into the progressive video signals on a pixel interpolative basis when the interlaced signals meet neither the first standard nor the second standard.
摘要翻译：即使在基于视频传输序列的视频信号和不基于视频传输序列的视频信号之间的差异是模糊的情况下，也能适用于每个视频信号的逐行合成处理。根据本发明的转换装置检测是否基于视频传输序列输入的隔行视频信号是视频信号的评估结果是否符合第一标准和第二标准，将隔行扫描视频信号转换成当检测到隔行信号满足第一标准时，基于视频传输顺序的逐行视频信号，当检测到隔行扫描信号不满足第一标准时，以像素选择为基础将隔行扫描视频信号转换成逐行视频信号，但是满足第二标准，并且当隔行信号既不符合第一标准也不满足第二标准时，以像素插值为基础将隔行信号转换为逐行视频信号。

7. 发明授权

US06292881B1 Microprocessor, operation process execution method and recording medium 有权
标题翻译：微处理器，操作过程执行方法和记录介质
公开(公告)号：US06292881B1
公开(公告)日：2001-09-18
申请号：US09257198
申请日：1999-02-25
申请人： Ritsuko Tanaka , Yuji Nomura , Toru Tsuruta , Nobuyuki Iwasaki
发明人： Ritsuko Tanaka , Yuji Nomura , Toru Tsuruta , Nobuyuki Iwasaki
IPC分类号： G06F940
CPC分类号： G06F9/3017 , G06F9/30145
摘要： A microprocessor capable of executing a process instruction having at least one RISC type instruction is constructed to include an instruction decoding section for decoding a microcode including information which indicates transfer contents of input and output data and address information which indicates a storage location of the process instruction, a data reading section for reading input data corresponding to the information which indicates the transfer contents of the input and output data decoded by the instruction decoding section and reading the process instruction corresponding to the address information, and an operation process executing section for implementing one or a plurality of operation unit resources capable of executing an operation process according to the input data read by the data reading section and the process instruction.
摘要翻译：能够执行具有至少一个RISC型指令的处理指令的微处理器被构造成包括用于解码包括指示输入和输出数据的传送内容的信息的微码的指令解码部分和指示处理指令的存储位置的地址信息数据读取部分，用于读取对应于指示由指令解码部分解码的输入和输出数据的传送内容并且读取对应于地址信息的处理指令的信息的输入数据;以及操作处理执行部分，用于实现一个或能够根据由数据读取部读取的输入数据和处理指令执行动作处理的多个操作部资源。

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