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11. 发明申请

US20120018790A1 NON-VOLATILE MEMORY AND FABRICATING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20120018790A1
公开(公告)日：2012-01-26
申请号：US12839559
申请日：2010-07-20
申请人： SHIH-GUEI YAN , Wen-Jer Tsai , Jyun-Siang Huang
发明人： SHIH-GUEI YAN , Wen-Jer Tsai , Jyun-Siang Huang
IPC分类号： H01L29/788 , H01L21/336 , H01L29/792
CPC分类号： H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/792
摘要： A non-volatile memory including a substrate, a stacked gate structure, two doped regions and a plurality of spacers is provided. The stacked gate structure is disposed on the substrate, wherein the stacked gate structure includes a first dielectric layer, a charge storage layer, a second dielectric layer and a conductive layer in sequence from bottom to top relative to the substrate. The doped regions are disposed in the substrate at two sides of the stacked gate structure, respectively, and bottom portions of the doped regions contact with the substrate under the doped regions. The spacers are respectively disposed between each side of each of the doped regions and the substrate, and top portions of the spacers are lower than top portions of the doped regions.
摘要翻译：提供包括衬底，堆叠栅极结构，两个掺杂区域和多个间隔物的非易失性存储器。堆叠的栅极结构设置在衬底上，其中堆叠的栅极结构包括从底部到顶部相对于衬底的顺序的第一介电层，电荷存储层，第二介电层和导电层。掺杂区域分别设置在堆叠栅极结构的两侧的衬底中，并且掺杂区域的底部部分在掺杂区域下与衬底接触。间隔物分别设置在每个掺杂区域和衬底的每一侧之间，并且间隔物的顶部部分低于掺杂区域的顶部部分。

12. 发明授权

US08569822B2 Memory structure 有权
标题翻译：内存结构
公开(公告)号：US08569822B2
公开(公告)日：2013-10-29
申请号：US13287728
申请日：2011-11-02
申请人： Jyun-Siang Huang , Wen-Jer Tsai , Shih-Guei Yan
发明人： Jyun-Siang Huang , Wen-Jer Tsai , Shih-Guei Yan
IPC分类号： H01L29/76 , H01L29/792
CPC分类号： H01L29/42332 , H01L27/11521 , H01L27/11568 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A memory structure having a memory cell including a first dielectric layer, a gate, a semiconductor layer, a first doped region, a second doped region and a charge storage layer is provided. The first dielectric layer is on the substrate. The gate includes a base portion on the first dielectric layer and a protruding portion disposed on the base portion and partially exposing the base portion. The semiconductor layer is conformally disposed on the gate, and includes a top portion over the protruding portion, a bottom portion over the base portion exposed by the protruding portion and a side portion located at a sidewall of the protruding portion and connecting the top and bottom portions. The first and second doped regions are respectively in the top and bottom portions. The side portion serves as a channel region. The charge storage layer is between the gate and the semiconductor layer.
摘要翻译：提供了具有包括第一介电层，栅极，半导体层，第一掺杂区域，第二掺杂区域和电荷存储层的存储单元的存储器结构。第一介电层位于基板上。所述栅极包括在所述第一介电层上的基部和设置在所述基部上的部分露出所述基部的突出部。所述半导体层保形地设置在所述栅极上，并且包括在所述突出部分之上的顶部，所述基部上的由所述突出部分露出的底部和位于所述突出部分的侧壁处的侧部，并且将所述顶部和底部部分。第一和第二掺杂区分别位于顶部和底部。侧部用作沟道区域。电荷存储层位于栅极和半导体层之间。

13. 发明授权

US09209316B2 ROM for constraining 2nd-bit effect 有权
标题翻译： ROM限制第二位效果
公开(公告)号：US09209316B2
公开(公告)日：2015-12-08
申请号：US13421389
申请日：2012-03-15
申请人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L27/115 , H01L29/792 , G11C11/56 , G11C16/04
CPC分类号： H01L29/792 , G11C11/5621 , G11C16/0466 , H01L27/11521 , H01L27/11568
摘要： A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.
摘要翻译：提供了包括基板，源极区和漏极区，电荷存储结构，栅极和局部极化掺杂区域的只读存储器。源极区域和漏极区域设置在衬底中，电荷存储结构位于源极区域和漏极区域之间的衬底上，并且栅极被配置在电荷存储结构上。局部极掺杂区位于源区和漏区之间的衬底中，并且包括低掺杂浓度区和至少一个高掺杂浓度区。高掺杂浓度区域设置在低掺杂浓度区域和源极区域和漏极区域之一中，并且高掺杂浓度区域的掺杂浓度是低掺杂浓度的掺杂浓度的三倍或更多倍地区。

14. 发明申请

US20130240975A1 ROM FOR CONSTRAINING 2nd-BIT EFFECT 有权
标题翻译：用于约束第二位影响的ROM
公开(公告)号：US20130240975A1
公开(公告)日：2013-09-19
申请号：US13421389
申请日：2012-03-15
申请人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
发明人： Chih-Chieh Cheng , Cheng-Hsien Cheng , Wen-Jer Tsai
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , G11C11/5621 , G11C16/0466 , H01L27/11521 , H01L27/11568
摘要： A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.
摘要翻译：提供了包括基板，源极区和漏极区，电荷存储结构，栅极和局部极化掺杂区域的只读存储器。源极区域和漏极区域设置在衬底中，电荷存储结构位于源极区域和漏极区域之间的衬底上，并且栅极被配置在电荷存储结构上。局部极掺杂区位于源区和漏区之间的衬底中，并且包括低掺杂浓度区和至少一个高掺杂浓度区。高掺杂浓度区域设置在低掺杂浓度区域和源极区域和漏极区域之一中，并且高掺杂浓度区域的掺杂浓度是低掺杂浓度的掺杂浓度的三倍或更多倍地区。

15. 发明授权

US08218364B2 Operation methods for memory cell and array for reducing punch through leakage 有权
标题翻译：用于减少穿孔渗漏的存储单元和阵列的操作方法
公开(公告)号：US08218364B2
公开(公告)日：2012-07-10
申请号：US13159413
申请日：2011-06-13
申请人： Lit-Ho Chong , Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
发明人： Lit-Ho Chong , Wen-Jer Tsai , Tien-Fan Ou , Jyun-Siang Huang
IPC分类号： G11C11/34
CPC分类号： G11C5/04 , G11C16/0416 , G11C16/10 , H01L27/11521 , H01L27/11568
摘要： An integrated circuit includes a memory array having a plurality of memory cells arranged in rows and columns, each memory cell including two doped regions and a channel region therebetween, each pair of adjacent memory cells sharing a common doped region, each memory cell having a charge storage member over the channel region and a control gate over the charge storage member. A first word line is coupled to the memory cells in the same row, each of the memory cells designated as the Nth memory cell. Each of a plurality of bit lines is designated as the Nth bit line, the Nth bit line coupled to a doped region shared by the Nth memory cell and the (N−1)th memory cell. The integrated circuit also has a plurality of global bit lines, each of which coupled to two of the bit lines via a switch.
摘要翻译：集成电路包括具有以行和列排列的多个存储单元的存储器阵列，每个存储单元包括两个掺杂区和它们之间的沟道区，每对相邻的存储单元共用公共掺杂区，每个存储单元具有一个电荷存储部件，以及位于电荷存储部件上的控制栅极。第一字线耦合到相同行中的存储器单元，每个存储器单元被指定为第N个存储器单元。多个位线中的每一行被指定为第N位线，第N位线耦合到由第N存储器单元和第（N-1）个存储器单元共享的掺杂区域。集成电路还具有多个全局位线，每个位线经由开关耦合到两个位线。

16. 发明申请

US20110305088A1 HOT CARRIER PROGRAMMING IN NAND FLASH 有权
标题翻译： NAND FLASH中的热载体编程
公开(公告)号：US20110305088A1
公开(公告)日：2011-12-15
申请号：US12797994
申请日：2010-06-10
申请人： JYUN-SIANG HUANG , Wen-Jer Tsai
发明人： JYUN-SIANG HUANG , Wen-Jer Tsai
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C16/3418
摘要： A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field. Boosted channel hot carrier injection can be based on blocking flow of carriers between a first side of a selected cell and a second side of the selected cell in the NAND string, boosting by capacitive coupling the first semiconductor body region to a boosted voltage level, biasing the second semiconductor body region to a reference voltage level, applying a program potential greater than a hot carrier injection barrier level to the selected cell and enabling flow of carriers from the second semiconductor body region to the selected cell to cause generation of hot carriers.
摘要翻译：存储器件包括串联布置在半导体本体中的多个存储单元，例如具有多个字线的NAND串。通过使用升压通道电位的热载流子注入来对选定的存储单元进行编程以建立加热场。升压通道热载流子注入可以基于阻塞NAND串中选定单元的第一侧和所选单元的第二侧之间的载流子的流动，通过将第一半导体体区域电容耦合到提升的电压电平来提升将第二半导体主体区域设置为参考电压电平，将大于热载流子注入势垒级的编程电位施加到所选择的单元，并且使载流子能够从第二半导体体区域流向所选择的单元以引起热载流子的产生。

17. 发明授权

US07916551B2 Method of programming cell in memory and memory apparatus utilizing the method 有权
标题翻译：利用该方法在存储器和存储装置中编程单元的方法
公开(公告)号：US07916551B2
公开(公告)日：2011-03-29
申请号：US12138707
申请日：2008-06-13
申请人： Wen-Jer Tsai , Ta-Hui Wang , Chih-Wei Lee
发明人： Wen-Jer Tsai , Ta-Hui Wang , Chih-Wei Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/10
摘要： A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/D region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell.
摘要翻译：一种对存储器中的第一单元进行编程的方法，其中所述第一单元具有第一S / D区域并与具有与所述第二S / D区域相反的第三S / D区域的第二单元共享第二S / D区域。第一单元和第二单元的通道导通，第一电压施加到第一S / D区，第二电压施加到第二S / D区，第三电压施加到第三S / D区地区。第二电压在第一电压和第三电压之间，并且第一至第三电压使载流子从第三S / D区流向第一S / D区，并使第一电池的通道中的热载流子注入进入第一电池的电荷存储层。

18. 发明申请

US20080164523A1 DYNAMIC RANDOM ACCESS MEMORY CELL AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：动态随机访问存储单元及其制造方法
公开(公告)号：US20080164523A1
公开(公告)日：2008-07-10
申请号：US11619663
申请日：2007-01-04
申请人： Ta-Wei Lin , Wen-Jer Tsai
发明人： Ta-Wei Lin , Wen-Jer Tsai
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L27/10802 , H01L21/84 , H01L27/10844 , H01L27/1203 , H01L29/7841
摘要： A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.
摘要翻译：提供了一种动态随机存取存储单元及其制造方法。首先，提供形成有底部氧化物层和半导体层的基板。半导体层形成在底部氧化物层上。接下来，在半导体层上形成栅极。然后，对半导体层进行图案化以暴露底部氧化物层的一部分。之后，在半导体层的侧壁形成绝缘层，其中绝缘层的高度比半导体层的高度短，从而在绝缘层的顶部和半导体层之间形成间隙。此外，在底部氧化物层上形成覆盖绝缘层并且与半导体层具有相同高度的掺杂层。掺杂层经由间隙与半导体层的侧壁接触。

19. 外观设计

USD490430S1 Keyboard 失效
公开(公告)号：USD490430S1
公开(公告)日：2004-05-25
申请号：US29173199
申请日：2002-12-26
申请人： Wen-Jer Tsai
设计人： Wen-Jer Tsai

20. 发明授权

US06512710B1 Reliability test method and circuit for non-volatile memory 有权
标题翻译：非易失性存储器的可靠性测试方法和电路
公开(公告)号：US06512710B1
公开(公告)日：2003-01-28
申请号：US10004636
申请日：2001-12-04
申请人： Wen-Jer Tsai , Lan Ting Huang , Nian-Kai Zous , Ta-Hui Wang
发明人： Wen-Jer Tsai , Lan Ting Huang , Nian-Kai Zous , Ta-Hui Wang
IPC分类号： G11C700
CPC分类号： G11C29/50016 , G11C8/08 , G11C16/04 , G11C29/50
摘要： A reliability test method for a non-volatile memory. A relation curve of gate voltage versus read current degradation rate is obtained. The read current degradation rate of an actual gate voltage is estimated. From the relation curve, an accelerated test gate voltage and a test time corresponding to the actual gate voltage are obtained. With the accelerated test gate voltage, the test is continuously performed within the test time. Afterward, a test result of the memory is then obtained and, by the result, it is judged whether the data is valid or not. If the data is right (retained), the memory can be guarantied to have an expected lifetime; if the data is wrong (lost), the memory is judged as fails to pass the lifetime test.
摘要翻译：用于非易失性存储器的可靠性测试方法。获得栅极电压与读取电流退化率的关系曲线。估计实际栅极电压的读取电流劣化率。从关系曲线可以得到与实际栅极电压对应的加速测试栅极电压和测试时间。加速测试门电压，测试在测试时间内连续进行。然后，获得存储器的测试结果，并且通过结果判断数据是否有效。如果数据正确（保留），则可以保证存储器具有预期的使用寿命; 如果数据错误（丢失），则存储器被判定为无法通过寿命测试。

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