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11. 发明授权

US09095170B2 Apparatus and method for manufacturing pet food 有权
标题翻译：制造宠物食品的设备和方法
公开(公告)号：US09095170B2
公开(公告)日：2015-08-04
申请号：US13368183
申请日：2012-02-07
申请人： Yoshiharu Okamoto , Masayuki Tajiri
发明人： Yoshiharu Okamoto , Masayuki Tajiri
IPC分类号： A23N17/00 , A23K1/00 , A23K1/18
CPC分类号： A23N17/004 , A23K40/20 , A23K40/25 , A23K50/40 , A23N17/005
摘要： A manufacturing apparatus and a manufacturing method of pet food are provided. The manufacturing apparatus comprises a material inlet through which a kneaded material is fed, the kneaded material being obtained through kneading a raw pet food material; an extrusion molding section configured to extrude the kneaded material through an extruding outlet; a cutter configured to cut the kneaded material extruded through the extruding outlet at desired intervals to form material grains; a reservoir disposed in a location to receive the material grains falling due to the cutting; an agitating section provided in the reservoir and configured to agitate the material grains; a heating section configured to heat the material grains while the material grains are agitated by the agitating section; and a drying section configured to dry the material grains within the reservoir after the heating.
摘要翻译：提供宠物食品的制造装置和制造方法。该制造装置包括通过捏合原料的宠物食材得到的捏合材料的材料入口，挤出成形部，其构造成通过挤压出口挤出混炼物; 切割器，其被构造成以期望的间隔切割通过挤出出口挤出的捏合材料以形成材料颗粒; 设置在容纳由于切割而落下的材料颗粒的位置的储存器; 搅拌部，设置在所述储存器中并且构造成搅拌所述材料颗粒; 加热部，其构造成在所述搅拌部搅拌所述材料粒子的同时加热所述材料粒子; 以及干燥部，其被配置为在加热之后干燥储存器内的材料颗粒。

12. 发明申请

US20060154417A1 Semiconductor memory device 审中-公开
标题翻译：半导体存储器件
公开(公告)号：US20060154417A1
公开(公告)日：2006-07-13
申请号：US11330806
申请日：2006-01-11
申请人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
发明人： Naoyuki Shinmura , Shigeo Ohnishi , Tetsuya Ohnishi , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri
IPC分类号： H01L21/8242
CPC分类号： H01L45/1675 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1641
摘要： The present invention is directed towards a method of manufacturing a semiconductor memory device arranged of a cross point memory array having memory elements provided between upper and lower electrodes for storage of data. The present invention comprises a lower electrode lines forming step of planarizing each of the lower electrode lines and insulating layers provided on both sides of the lower electrode line so as to be substantially uniform in the height thus for patterning the lower electrode lines, a memory element layer depositing step of depositing on the lower electrode lines a memory element layer for the memory elements, and an annealing step of annealing with heat treatment either between the lower electrode lines forming step and the memory element layer depositing step or after the memory element layer depositing step so that any damages caused by the polishing of the surface of the lower electrode lines can be eliminated.
摘要翻译：本发明涉及一种制造半导体存储器件的方法，该半导体存储器件被布置成具有设置在上部和下部电极之间的存储元件的交叉点存储器阵列，用于存储数据。本发明包括下电极线，其形成步骤：将设置在下电极线两侧的每个下电极线和绝缘层平坦化，以使其高度大致均匀，从而构图下电极线;存储元件在下电极线上沉积用于存储元件的存储元件层的层沉积步骤，以及在下电极线形成步骤和存储元件层沉积步骤之间或在存储元件层沉积之后进行热处理退火的退火步骤使得可以消除由下电极线的表面的抛光引起的任何损坏。

13. 发明授权

US08541822B2 Semiconductor device and method for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08541822B2
公开(公告)日：2013-09-24
申请号：US12591340
申请日：2009-11-17
申请人： Masayuki Tajiri
发明人： Masayuki Tajiri
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L29/165 , H01L29/41783 , H01L29/665 , H01L29/66568
摘要： A semiconductor device comprising at least two wiring layers on a substrate or a surface layer of the substrate, wherein a lower wiring layer of the two wiring layers contains silicon, and a silicon carbide layer is placed between the lower wiring layer and an upper wiring layer.
摘要翻译：一种半导体器件，包括在衬底或衬底的表面层上的至少两个布线层，其中两个布线层的下布线层包含硅，并且碳化硅层位于下布线层和上布线层之间。

14. 发明授权

US08030695B2 Structure and manufacturing method of semiconductor memory device 有权
公开(公告)号：US08030695B2
公开(公告)日：2011-10-04
申请号：US12976113
申请日：2010-12-22
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L21/02
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.

15. 发明申请

US20110042730A1 Semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US20110042730A1
公开(公告)日：2011-02-24
申请号：US12805675
申请日：2010-08-12
申请人： Masayuki Tajiri , Takayoshi Hashimoto , Hisashi Yonemoto , Toyohiro Harazono
发明人： Masayuki Tajiri , Takayoshi Hashimoto , Hisashi Yonemoto , Toyohiro Harazono
IPC分类号： H01L29/772 , H01L21/762
CPC分类号： H01L21/76224 , H01L29/78
摘要： A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, an liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
摘要翻译：提供了可以形成具有优异特性的高压晶体管的元件隔离膜的形成方法。在基板上预先形成栅极氧化膜。在其上形成CMP阻挡膜，然后蚀刻栅极氧化膜和CMP阻挡膜。蚀刻半导体衬底以形成沟槽。此外，在沟槽填充有场绝缘膜之前，在沟槽内壁形成衬垫绝缘膜，在CMP阻挡膜下方的栅极氧化膜的侧面的凹部填充有衬垫绝缘膜。以这种方式，可以防止在相对于栅极氧化膜横向定位的元件隔离膜中形成空隙。

16. 发明授权

US07879626B2 Structure and manufacturing method of semiconductor memory device 有权
标题翻译：半导体存储器件的结构和制造方法
公开(公告)号：US07879626B2
公开(公告)日：2011-02-01
申请号：US11274258
申请日：2005-11-16
申请人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
发明人： Tetsuya Ohnishi , Naoyuki Shinmura , Shinobu Yamazaki , Takahiro Shibuya , Takashi Nakano , Masayuki Tajiri , Shigeo Ohnishi
IPC分类号： H01L21/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： A semiconductor memory device having a cross point structure includes a plurality of upper electrodes arranged to extend in one direction, and a plurality of lower electrodes arranged to extend in another direction at a right angle to the one direction of the upper electrodes. Memory materials are provided between the upper electrodes and the lower electrodes for storage of data. The memory materials are made of a perovskite material and arranged at the lower electrodes side of the corresponding upper electrode extending along the corresponding upper electrode.
摘要翻译：具有交叉点结构的半导体存储器件包括沿一个方向延伸的多个上电极和布置成沿与上电极的一个方向成直角的另一方向延伸的多个下电极。记录材料设置在上电极和下电极之间用于存储数据。记忆材料由钙钛矿材料制成，并且布置在沿着相应的上电极延伸的相应上电极的下电极侧。

17. 发明申请

US20100127310A1 Semiconductor device and method for producing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20100127310A1
公开(公告)日：2010-05-27
申请号：US12591340
申请日：2009-11-17
申请人： Masayuki Tajiri
发明人： Masayuki Tajiri
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L29/165 , H01L29/41783 , H01L29/665 , H01L29/66568
摘要： A semiconductor device comprising at least two wiring layers on a substrate or a surface layer of the substrate, wherein a lower wiring layer of the two wiring layers contains silicon, and a silicon carbide layer is placed between the lower wiring layer and an upper wiring layer.
摘要翻译：一种半导体器件，包括在衬底或衬底的表面层上的至少两个布线层，其中两个布线层的下布线层包含硅，并且碳化硅层位于下布线层和上布线层之间。

18. 发明授权

US07668001B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07668001B2
公开(公告)日：2010-02-23
申请号：US11921755
申请日：2006-01-05
申请人： Masayuki Tajiri , Atsushi Shimaoka , Kohji Inoue
发明人： Masayuki Tajiri , Atsushi Shimaoka , Kohji Inoue
IPC分类号： G11C11/00
CPC分类号： G11C13/00 , G11C13/0023 , G11C13/0069 , G11C2013/009 , G11C2213/77
摘要： A semiconductor memory device (1) comprises a memory cell array (100) in which memory cells each have a variable resistance element and the memory cells in the same row are connected to a common word line and the memory cells in the same column are connected to a common bit line, wherein during a predetermined memory action, the voltage amplitude of the voltage pulse applied to an end of at least one of the selected word line and the selected bit line is adjusted based on the position of the selected memory cell in the memory cell array (100) so that the effective voltage amplitude of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased falls within a certain range regardless of the position in the memory cell array (100).
摘要翻译：半导体存储器件（1）包括存储单元阵列（100），其中存储单元各自具有可变电阻元件，并且同一行中的存储单元连接到公共字线，并且同一列中的存储器单元被连接公共位线，其中在预定的存储器动作期间，基于所选择的存储器单元的位置来调整施加到所选字线和所选位线中的至少一个的末端的电压脉冲的电压幅度存储单元阵列（100），使得施加到要编程或擦除的所选存储单元的可变电阻元件的电压脉冲的有效电压幅度落在一定范围内，而与存储单元阵列（100）中的位置无关，。

19. 发明授权

US08482074B2 Semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US08482074B2
公开(公告)日：2013-07-09
申请号：US13137599
申请日：2011-08-29
申请人： Masayuki Tajiri , Takayoshi Hashimoto , Hisashi Yonemoto , Toyohiro Harazono
发明人： Masayuki Tajiri , Takayoshi Hashimoto , Hisashi Yonemoto , Toyohiro Harazono
IPC分类号： H01L29/78
CPC分类号： H01L21/76224 , H01L29/78
摘要： A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, a liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
摘要翻译：提供了可以形成具有优异特性的高压晶体管的元件隔离膜的形成方法。在基板上预先形成栅极氧化膜。在其上形成CMP阻挡膜，然后蚀刻栅极氧化膜和CMP阻挡膜。蚀刻半导体衬底以形成沟槽。此外，在沟槽填充有场绝缘膜之前，在沟槽内壁形成有衬垫绝缘膜，在CMP阻挡膜下方的栅极氧化膜的侧面的凹部填充有衬垫绝缘膜。以这种方式，可以防止在相对于栅极氧化膜横向定位的元件隔离膜中形成空隙。

20. 发明申请

US20120139052A1 Semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US20120139052A1
公开(公告)日：2012-06-07
申请号：US13137599
申请日：2011-08-29
申请人： Masayuki Tajiri , Takayoshi Hashimoto , Hisashi Yonemoto , Toyohiro Harazono
发明人： Masayuki Tajiri , Takayoshi Hashimoto , Hisashi Yonemoto , Toyohiro Harazono
IPC分类号： H01L29/06
CPC分类号： H01L21/76224 , H01L29/78
摘要： A formation method of an element isolation film according to which a high-voltage transistor with an excellent characteristic can be formed is provided. On a substrate, a gate oxide film is previously formed. A CMP stopper film is formed thereon, and thereafter, a gate oxide film and a CMP stopper film are etched. The semiconductor substrate is etched to form a trench. Further, before the trench is filled with a field insulating film, a liner insulating film is formed at a trench interior wall, and a concave portion at the side surface of the gate oxide film under the CMP stopper film is filled with the liner insulating film. In this manner, formation of void in the element isolation film laterally positioned with respect to the gate oxide film can be prevented.
摘要翻译：提供了可以形成具有优异特性的高压晶体管的元件隔离膜的形成方法。在基板上预先形成栅极氧化膜。在其上形成CMP阻挡膜，然后蚀刻栅极氧化膜和CMP阻挡膜。蚀刻半导体衬底以形成沟槽。此外，在沟槽填充有场绝缘膜之前，在沟槽内壁形成有衬垫绝缘膜，在CMP阻挡膜下方的栅极氧化膜的侧面的凹部填充有衬垫绝缘膜。以这种方式，可以防止在相对于栅极氧化膜横向定位的元件隔离膜中形成空隙。

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