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11. 发明授权

US09165918B1 Composite semiconductor device with multiple threshold voltages 有权
标题翻译：具有多个阈值电压的复合半导体器件
公开(公告)号：US09165918B1
公开(公告)日：2015-10-20
申请号：US14272027
申请日：2014-05-07
申请人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Pete Rodriguez , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/66 , H01L27/02 , H01L29/78 , H01L29/08 , H01L29/10 , H01L27/088 , H01L21/8234 , H01L21/265
CPC分类号： H01L27/0248 , H01L21/26513 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L27/0266 , H01L27/088 , H01L29/0653 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1045 , H01L29/1079 , H01L29/1095 , H01L29/66575 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A device includes a semiconductor substrate, a first constituent transistor including a first plurality of transistor structures in the semiconductor substrate connected in parallel with one another, and a second constituent transistor including a second plurality of transistor structures in the semiconductor substrate connected in parallel with one another. The first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel with one another. Each transistor structure of the first plurality of transistor structures includes a non-uniform channel such that the first constituent transistor has a higher threshold voltage level than the second constituent transistor.
摘要翻译：一种器件包括半导体衬底，第一组成晶体管，其包括彼此并联连接的半导体衬底中的第一多个晶体管结构;以及第二组成晶体管，包括在半导体衬底中并联连接的第二多个晶体管结构，另一个。第一和第二组成晶体管彼此横向相邻设置并彼此并联连接。第一多个晶体管结构的每个晶体管结构包括非均匀沟道，使得第一构成晶体管具有比第二构成晶体管更高的阈值电压电平。

12. 发明授权

US09159803B2 Semiconductor device with HCI protection region 有权
标题翻译：具有HCI保护区的半导体器件
公开(公告)号：US09159803B2
公开(公告)日：2015-10-13
申请号：US13590995
申请日：2012-08-21
申请人： Won Gi Min , Hongning Yang , Jiangkai Zuo
发明人： Won Gi Min , Hongning Yang , Jiangkai Zuo
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/40 , H01L29/08 , H01L29/10
CPC分类号： H01L29/66659 , H01L29/0619 , H01L29/063 , H01L29/0646 , H01L29/0653 , H01L29/0847 , H01L29/1083 , H01L29/402 , H01L29/7835
摘要： A device includes a semiconductor substrate, a drift region in the semiconductor substrate and having a first conductivity type, an isolation region within the drift region, and around which charge carriers drift on a path through the drift region during operation, and a protection region adjacent the isolation region in the semiconductor substrate, having a second conductivity type, and disposed along a surface of the semiconductor substrate.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的漂移区，并具有第一导电类型，漂移区内的隔离区，电荷载流子在工作期间通过漂移区的路径漂移，以及相邻的保护区具有第二导电类型的半导体衬底中的隔离区域，并沿着半导体衬底的表面设置。

13. 发明授权

US09136323B2 Drain-end drift diminution in semiconductor devices 有权
标题翻译：半导体器件的漏极漂移减少
公开(公告)号：US09136323B2
公开(公告)日：2015-09-15
申请号：US14486104
申请日：2014-09-15
申请人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/06 , H01L29/66 , H01L29/78 , H01L29/08 , H01L29/10
CPC分类号： H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
摘要翻译：制造晶体管的方法包括在衬底中形成场隔离区域。在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。漏极区形成在衬底的第二区域中。第一和第二区域横向重叠以限定晶体管的导电路径。第一区域不横向跨越第二区域延伸。

14. 发明申请

US20150056751A1 DIE EDGE SEALING STRUCTURES AND RELATED FABRICATION METHODS 有权
标题翻译： DIE边缘密封结构和相关制造方法
公开(公告)号：US20150056751A1
公开(公告)日：2015-02-26
申请号：US14505842
申请日：2014-10-03
申请人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
发明人： Zhihong Zhang , Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L23/00 , H01L21/78
CPC分类号： H01L23/562 , H01L21/78 , H01L23/3171 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Die structures for electronic devices and related fabrication methods are provided. An exemplary die structure includes a diced portion of a semiconductor substrate that includes a device region having one or more semiconductor devices fabricated thereon and an edge sealing structure within the semiconductor substrate that circumscribes the device region. In one or more embodiments, the edge sealing structure includes a conductive material that contacts a handle layer of semiconductor material, a crackstop structure is formed overlying the sealing structure, wherein the crackstop structure and the edge sealing structure provide an electrical connection between the handle layer and an active layer of semiconductor material that overlies a buried layer of dielectric material on the handle layer.
摘要翻译：提供电子器件的模具结构和相关的制造方法。示例性的管芯结构包括半导体衬底的切割部分，其包括其上制造有一个或多个半导体器件的器件区域和在该半导体衬底内限定器件区域的边缘密封结构。在一个或多个实施例中，边缘密封结构包括接触半导体材料的手柄层的导电材料，形成在密封结构上方的裂缝结构，其中裂缝结构和边缘密封结构在手柄层之间提供电连接以及覆盖在手柄层上的介电材料的掩埋层的半导体材料的有源层。

15. 发明申请

US20150004768A1 DRAIN-END DRIFT DIMINUTION IN SEMICONDUCTOR DEVICES 有权
标题翻译：半导体器件中的引出端DRIFT分解
公开(公告)号：US20150004768A1
公开(公告)日：2015-01-01
申请号：US14486104
申请日：2014-09-15
申请人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
发明人： Hongning Yang , Daniel J. Blomberg , Xu Cheng , Xin Lin , Won Gi Min , Zhihong Zhang , Jiang-Kai Zuo
IPC分类号： H01L29/06 , H01L29/66 , H01L29/10
CPC分类号： H01L29/063 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： A method of fabricating a transistor includes forming a field isolation region in a substrate. After forming the field isolation region, dopant is implanted in a first region of a substrate for formation of a drift region. A drain region is formed in a second region of the substrate. The first and second regions laterally overlap to define a conduction path for the transistor. The first region does not extend laterally across the second region.
摘要翻译：制造晶体管的方法包括在衬底中形成场隔离区域。在形成场隔离区之后，将掺杂剂注入到用于形成漂移区的衬底的第一区域中。漏极区形成在衬底的第二区域中。第一和第二区域横向重叠以限定晶体管的导电路径。第一区域不横向跨越第二区域延伸。

16. 发明授权

US08652930B2 Semiconductor device with self-biased isolation 有权
标题翻译：具有自偏置隔离的半导体器件
公开(公告)号：US08652930B2
公开(公告)日：2014-02-18
申请号：US13973230
申请日：2013-08-22
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L21/76
CPC分类号： H01L29/063 , H01L21/761 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/1083 , H01L29/423 , H01L29/66659 , H01L29/7835
摘要： A method of fabricating a reduced surface field (RESURF) transistor includes forming a first well in a substrate, the first well having a first conductivity type, doping a RESURF region of the first well to have a second conductivity type, doping a portion of the first well to form a drain region of the RESURF transistor, the drain region having the first conductivity type, and forming a second well in the substrate, the second well having the second conductivity type. A plug region is formed in the substrate, the plug region extending to the RESURF region.
摘要翻译：制造还原表面场（RESURF）晶体管的方法包括在衬底中形成第一阱，第一阱具有第一导电类型，掺杂第一阱的RESURF区以具有第二导电类型，掺杂部分第一阱以形成RESURF晶体管的漏极区，漏区具有第一导电类型，并且在衬底中形成第二阱，第二阱具有第二导电类型。插塞区域形成在衬底中，插塞区域延伸到RESURF区域。

17. 发明授权

US08575692B2 Near zero channel length field drift LDMOS 有权
标题翻译：近零通道长度场漂移LDMOS
公开(公告)号：US08575692B2
公开(公告)日：2013-11-05
申请号：US13025350
申请日：2011-02-11
申请人： Hongning Yang , Xin Lin , Jiang-Kai Zuo
发明人： Hongning Yang , Xin Lin , Jiang-Kai Zuo
IPC分类号： H01L29/78
CPC分类号： H01L29/66681 , H01L21/26586 , H01L29/0653 , H01L29/086 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/66689 , H01L29/7801 , H01L29/7816
摘要： Adverse tradeoff between BVDSS and Rdson in LDMOS devices employing a drift space (52, 152) adjacent the drain (56, 156), is avoided by providing a lightly doped region (511, 1511) of a first conductivity type (CT) separating the first CT drift space (52, 152) from an opposite CT WELL region (53, 153) in which the first CT source (57, 157) is located, and a further region (60, 160) of the opposite CT (e.g., formed by an angled implant) extending through part of the WELL region (53, 153) under an edge (591, 1591) of the gate (59, 159) located near a boundary (531, 1531) of the WELL region (53, 153) into the lightly doped region (511, 1511), and a shallow still further region (66, 166) of the first CT Ohmically coupled to the source (57, 157) and ending near the gate edge (591, 159) whereby the effective channel length (61, 161) in the further region (60, 160) is reduced to near zero. Substantial improvement in BVDSS and/or Rdson can be obtained without degrading the other or significant adverse affect on other device properties.
摘要翻译：通过提供第一导电类型（CT）的轻掺杂区域（511,1511）来避免使用邻近漏极（56,156）的漂移空间（52,152）的LDMOS器件中的BVDSS和Rdson之间的不利权衡，从第一CT源（57,157）所在的相对的CT WELL区域（53,153）的第一CT漂移空间（52,152）和相对CT的另一区域（60,160）由位于靠近所述WELL区域（53,153）的边界（531,1531）附近的所述门（59,159）的边缘（591,1591）下延伸穿过所述WELL区域（53,153）的一部分的一部分， 153和157）连接到所述源极（57,157）并且在所述栅极边缘（591,159）附近结束的所述第一CT的浅的另外的区域（66,166），由此另一区域（60,160）中的有效通道长度（61,161）减小到接近零。可以获得BVDSS和/或Rdson的显着改善，而不会降低对其他设备性能的其他影响或显着的不利影响。

18. 发明授权

US08227861B2 Multi-gate semiconductor devices 有权
标题翻译：多栅极半导体器件
公开(公告)号：US08227861B2
公开(公告)日：2012-07-24
申请号：US12975808
申请日：2010-12-22
申请人： Hongning Yang , Xin Lin , Jiang-Kia Zuo
发明人： Hongning Yang , Xin Lin , Jiang-Kia Zuo
IPC分类号： H01L21/70
CPC分类号： H01L29/66484 , H01L29/1041 , H01L29/7831 , H01L29/7833
摘要： A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions.
摘要翻译：半导体器件包括衬底，形成在衬底上的源极区域，形成在衬底上的漏极区域，与衬底相邻的源极区域和源极区域与漏极区域之间的第一栅电极，以及位于源极区域和漏极区域之间的第二栅电极，衬底，其与漏极区域相邻并且在源极和漏极区域之间。

19. 发明申请

US20110169078A1 SWITCH MODE CONVERTER EMPLOYING DUAL GATE MOS TRANSISTOR 有权
标题翻译：使用双栅极MOS晶体管的开关模式转换器
公开(公告)号：US20110169078A1
公开(公告)日：2011-07-14
申请号：US13069158
申请日：2011-03-22
申请人： Hongning Yang , Jiang-Kai Zuo
发明人： Hongning Yang , Jiang-Kai Zuo
IPC分类号： H01L29/78
CPC分类号： H01L27/0705 , H01L29/1045 , H01L29/1083 , H01L29/402 , H01L29/41775 , H01L29/66659 , H01L29/7831 , H01L29/7835
摘要： A disclosed power transistor, suitable for use in a switch mode converter that is operable with a switching frequency exceeding, for example, 5 MHz or more, includes a gate dielectric layer overlying an upper surface of a semiconductor substrate and first and second gate electrodes overlying the gate dielectric layer. The first gate electrode is laterally positioned overlying a first region of the substrate. The first substrate region has a first type of doping, which may be either n-type or p-type. A second gate electrode of the power transistor overlies the gate dielectric and is laterally positioned over a second region of the substrate. The second substrate region has a second doping type that is different than the first type. The transistor further includes a drift region located within the substrate in close proximity to an upper surface of the substrate and laterally positioned between the first and second substrate regions.
摘要翻译：适用于可以以超过例如5MHz或更大的开关频率工作的开关模式转换器的公开的功率晶体管包括覆盖在半导体衬底的上表面上的栅极电介质层和覆盖的半导体衬底的第一和第二栅电极栅介质层。第一栅电极横向定位成覆盖在衬底的第一区域上。第一衬底区域具有第一类型的掺杂，其可以是n型或p型。功率晶体管的第二栅电极覆盖栅极电介质，并且横向地位于衬底的第二区域上方。第二衬底区域具有与第一类型不同的第二掺杂类型。晶体管还包括位于衬底内的漂移区域，该漂移区域紧邻衬底的上表面并横向地位于第一和第二衬底区域之间。

20. 发明授权

US07776700B2 LDMOS device and method 有权
标题翻译： LDMOS设备和方法
公开(公告)号：US07776700B2
公开(公告)日：2010-08-17
申请号：US11650188
申请日：2007-01-04
申请人： Hongning Yang , Veronique C. Macary , Jiang-Kai Zuo
发明人： Hongning Yang , Veronique C. Macary , Jiang-Kai Zuo
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L21/26586 , H01L21/7624 , H01L29/1045 , H01L29/1083 , H01L29/66537 , H01L29/66659 , H01L29/7835
摘要： An N-channel device (40, 60) is described having a very lightly doped substrate (42) in which spaced-apart P (46) and N (44) wells are provided, whose lateral edges (461, 45) extending to the surface (47). The gate (56) overlies the surface (47) between the P (46) and N (44) wells. The P-well edge (461) adjacent the source (50) is substantially aligned with the left gate edge (561). The N-well edge (45) lies at or within the right gate edge (562), which is spaced a first distance (471) from the drain (48). The N-well (44) desirably includes a heavier doped region (62) in ohmic contact with the drain (48) and with its left edge (621) located about half way between the right gate edge (562) and the drain (48). A HALO implant pocket (52) is provided underlying the left gate edge (561) using the gate (56) as a mask. The resulting device (40, 60) operates at higher voltage with lower Rdson, less HCI and very low off-state leakage. P and N dopants are interchanged to provide P-channel devices.
摘要翻译：描述了具有非常轻掺杂的衬底（42）的N沟道器件（40,60），其中设置有间隔开的P（46）和N（44）阱，其侧边缘（461,45）延伸到表面（47）。栅极（56）覆盖在P（46）和N（44）孔之间的表面（47）上。与源极（50）相邻的P阱边缘（461）基本上与左边缘边缘（561）对准。所述N阱边缘（45）位于所述右边缘边缘（562）内或所述右边缘边缘（562）中，所述右边缘边缘（562）与所述漏极（48）间隔开第一距离（471）。 N阱（44）期望地包括与漏极（48）欧姆接触的较重的掺杂区域（62），并且其左边缘（621）位于右栅极边缘（562）和漏极（48）之间的大约一半处）。使用门（56）作为掩模，将HALO注入口袋（52）设置在左门边缘（561）下方。所得到的器件（40,60）在较高电压下工作，Rdson较低，HCI较少，非常低的截止状态泄漏。 P和N掺杂剂互换以提供P沟道器件。

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