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11. 发明授权

US07320913B2 Methods of forming split-gate non-volatile memory devices 失效
标题翻译：形成分闸非易失性存储器件的方法
公开(公告)号：US07320913B2
公开(公告)日：2008-01-22
申请号：US11368247
申请日：2006-03-03
申请人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

12. 发明申请

US20080093647A1 SPLIT GATE NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME 失效
标题翻译：分离栅非易失性存储器件及其形成方法
公开(公告)号：US20080093647A1
公开(公告)日：2008-04-24
申请号：US11957037
申请日：2007-12-14
申请人： Sung-Taeg KANG , Hyok-Ki Kwon , Bo Seo , Seung Yoon , Hee Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg KANG , Hyok-Ki Kwon , Bo Seo , Seung Yoon , Hee Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L29/66825
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

13. 发明申请

US20060046388A1 Nonvolatile semiconductor device and method of fabricating the same 有权
标题翻译：非易失性半导体器件及其制造方法
公开(公告)号：US20060046388A1
公开(公告)日：2006-03-02
申请号：US11214247
申请日：2005-08-29
申请人： Young-Sam Park , Seung-Beom Yoon , Jeong-Uk Han , Sung-Taeg Kang , Seung-Jin Yang
发明人： Young-Sam Park , Seung-Beom Yoon , Jeong-Uk Han , Sung-Taeg Kang , Seung-Jin Yang
IPC分类号： H01L21/336 , H01L21/3205 , H01L21/8238
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/66553 , H01L29/66795 , H01L29/7851 , H01L29/7853 , H01L29/7854 , H01L29/7881
摘要： A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.
摘要翻译：提供一种非易失性半导体器件及其制造方法。非易失性半导体器件包括形成在基板上的半导体本体，该半导体本体在一个方向上被延伸并且具有垂直于基板的主表面和细长方向的横截面，该横截面具有预定的曲率，设置在沟道区域上的隧道绝缘层，设置在隧道绝缘层上并与沟道区电绝缘的浮置栅极，设置在浮动栅极上的栅极间绝缘层，设置在栅极上的控制栅极绝缘层和与浮置栅极电绝缘的源极和漏极区域，其与控制栅极的两侧对准并形成在半导体本体内。

14. 发明授权

US07514739B2 Nonvolatile semiconductor device and method of fabricating the same 有权
标题翻译：非易失性半导体器件及其制造方法
公开(公告)号：US07514739B2
公开(公告)日：2009-04-07
申请号：US11687942
申请日：2007-03-19
申请人： Young-Sam Park , Seung-Beom Yoon , Jeong-Uk Han , Sung-Taeg Kang , Seung-Jin Yang
发明人： Young-Sam Park , Seung-Beom Yoon , Jeong-Uk Han , Sung-Taeg Kang , Seung-Jin Yang
IPC分类号： H01L29/76 , H01L29/788
CPC分类号： H01L29/7854 , H01L21/28273 , H01L29/42324 , H01L29/66553 , H01L29/66795 , H01L29/7851 , H01L29/7853 , H01L29/7881
摘要： A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region along the circumference of the semiconductor body, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, electrically insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate.
摘要翻译：堆叠型非易失性半导体器件包括：形成在基板上的存储器件，该存储器件包括在一个方向上延伸的半导体本体，具有垂直于主表面的横截面，具有预定曲率，半导体本体上沿着圆周的沟道区域，沟道区域上的隧道绝缘层，与沟道区绝缘的隧道绝缘层上的浮动栅极，浮置栅极上的高介电常数材料层，高介电常数材料层上的金属控制栅极，绝缘层浮置栅极，与半导体主体上的金属控制栅极相邻的源极和漏极区域，存储器件上的绝缘层和绝缘层上的导电层，以及形成在导电层上的存储器件，包括具有垂直于主表面的横截面在一个方向上延伸的半导体本体，具有预制件沿着半导体本体的圆周的通道区域，沟道区域上的隧道绝缘层，隧道绝缘层上的浮动栅极，与沟道区电绝缘，浮置栅极上的高介电常数材料层，在高介电常数材料层上的金属控制栅极，与浮动栅极绝缘，以及与金属控制栅极相邻的源极和漏极区域。

15. 发明申请

US20070164344A1 NONVOLATILE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：非挥发性半导体器件及其制造方法
公开(公告)号：US20070164344A1
公开(公告)日：2007-07-19
申请号：US11687942
申请日：2007-03-19
申请人： Young-Sam Park , Seung-Beom Yoon , Jeong-Uk Han , Sung-Taeg Kang , Seung-Jin Yang
发明人： Young-Sam Park , Seung-Beom Yoon , Jeong-Uk Han , Sung-Taeg Kang , Seung-Jin Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/7854 , H01L21/28273 , H01L29/42324 , H01L29/66553 , H01L29/66795 , H01L29/7851 , H01L29/7853 , H01L29/7881
摘要： A stack-type nonvolatile semiconductor device comprises a memory device formed on a substrate including a semiconductor body elongated in one direction, having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region on the semiconductor body along the circumference, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate on the semiconductor body, an inter-insulating layer on the memory device, and a conductive layer on the inter-insulating layer, and a memory device formed on the conductive layer including, a semiconductor body elongated in one direction having a cross section perpendicular to a main surface, having a predetermined curvature, a channel region along the circumference of the semiconductor body, a tunneling insulating layer on the channel region, a floating gate on the tunneling insulating layer, electrically insulated from the channel region, a high dielectric constant material layer on the floating gate, a metallic control gate on the high dielectric constant material layer, insulated from the floating gate, and source and drain regions adjacent to the metallic control gate.
摘要翻译：堆叠型非易失性半导体器件包括：形成在基板上的存储器件，该存储器件包括在一个方向上延伸的半导体本体，具有垂直于主表面的横截面，具有预定曲率，半导体本体上沿着圆周的沟道区域，沟道区域上的隧道绝缘层，与沟道区绝缘的隧道绝缘层上的浮动栅极，浮置栅极上的高介电常数材料层，高介电常数材料层上的金属控制栅极，绝缘层浮置栅极，与半导体主体上的金属控制栅极相邻的源极和漏极区域，存储器件上的绝缘层和绝缘层上的导电层，以及形成在导电层上的存储器件，包括具有垂直于主表面的横截面在一个方向上延伸的半导体本体，具有预制件沿着半导体本体的圆周的通道区域，沟道区域上的隧道绝缘层，隧道绝缘层上的浮动栅极，与沟道区电绝缘，浮置栅极上的高介电常数材料层，在高介电常数材料层上的金属控制栅极，与浮动栅极绝缘，以及与金属控制栅极相邻的源极和漏极区域。

16. 发明授权

US07820516B2 Methods of manufacturing non-volatile memory devices having a vertical channel 有权
标题翻译：制造具有垂直通道的非易失性存储器件的方法
公开(公告)号：US07820516B2
公开(公告)日：2010-10-26
申请号：US11798563
申请日：2007-05-15
申请人： Seung-Jin Yang , Hyok-ki Kwon , Yong-Seok Choi , Jeong-Uk Han
发明人： Seung-Jin Yang , Hyok-ki Kwon , Yong-Seok Choi , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L29/0692 , G11C16/0416 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.
摘要翻译：公开了一种半导体闪存单元，包括形成在半导体衬底中的第一和第二源极线，从源极线之间的衬底延伸的半导体柱，形成在半导体柱的相对侧表面上并由沟槽分隔的第一和第二电荷存储结构隔离结构。选择分离存储单元阵列中的相邻半导体柱的x和y间距，由此形成沟槽隔离结构用于分离电荷存储结构和设置在半导体柱的相对侧上的导电结构。还公开了制造这种结构的方法，由此可以提高闪存器件，特别是NOR闪存器件的密度。

17. 发明申请

US20080002475A1 Non-volatile memory devices having a vertical channel and methods of manufacturing such devices 有权
标题翻译：具有垂直通道的非易失性存储器件和制造这种器件的方法
公开(公告)号：US20080002475A1
公开(公告)日：2008-01-03
申请号：US11798563
申请日：2007-05-15
申请人： Seung-Jin Yang , Hyok-ki Kwon , Yong-Seok Choi , Jeong-Uk Han
发明人： Seung-Jin Yang , Hyok-ki Kwon , Yong-Seok Choi , Jeong-Uk Han
IPC分类号： G11C11/34 , H01L21/336
CPC分类号： H01L29/0692 , G11C16/0416 , H01L27/115 , H01L27/11556 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.
摘要翻译：公开了一种半导体闪存单元，包括形成在半导体衬底中的第一和第二源极线，从源极线之间的衬底延伸的半导体柱，形成在半导体柱的相对侧表面上并由沟槽分隔的第一和第二电荷存储结构隔离结构。选择分离存储单元阵列中的相邻半导体柱的x和y间距，由此形成沟槽隔离结构用于分离电荷存储结构和设置在半导体柱的相对侧上的导电结构。还公开了制造这种结构的方法，由此可以提高闪存器件，特别是NOR闪存器件的密度。

18. 发明申请

US20080268592A1 Flash memory device and method of fabricating the same 审中-公开
标题翻译：闪存装置及其制造方法
公开(公告)号：US20080268592A1
公开(公告)日：2008-10-30
申请号：US12004698
申请日：2007-12-21
申请人： Weon-Ho Park , Jeong-Uk Han , Yong-Tae Kim
发明人： Weon-Ho Park , Jeong-Uk Han , Yong-Tae Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7881
摘要： Provided are a flash memory device and a method of fabricating the same. The method includes forming a first dielectric layer on an active region of a semiconductor substrate. A first conductive layer is formed on the semiconductor substrate having the first dielectric layer. A mask pattern is formed on the first conductive layer. Using the mask pattern as an etch mask, the first conductive layer is etched to form a first conductive pattern narrowing from its upper surface toward its middle portion. A second dielectric layer is formed on the semiconductor substrate having the first conductive pattern. A second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern is formed on the semiconductor substrate having the second dielectric layer.
摘要翻译：提供一种闪速存储器件及其制造方法。该方法包括在半导体衬底的有源区上形成第一电介质层。在具有第一介电层的半导体衬底上形成第一导电层。在第一导电层上形成掩模图案。使用掩模图案作为蚀刻掩模，蚀刻第一导电层以形成从其上表面向其中间部分变窄的第一导电图案。在具有第一导电图案的半导体衬底上形成第二电介质层。在具有第二介电层的半导体衬底上形成与第一导电图案相邻的有源区域交叉并部分覆盖第一导电图案的第二导电图案。

19. 发明申请

US20080111181A1 Nonvolatile memory devices, methods of operating the same and methods of forming the same 审中-公开
标题翻译：非易失存储器件，其操作方法及其形成方法
公开(公告)号：US20080111181A1
公开(公告)日：2008-05-15
申请号：US11982036
申请日：2007-11-01
申请人： Weon-Ho Park , Jeong-Uk Han , Yong-Tae Kim
发明人： Weon-Ho Park , Jeong-Uk Han , Yong-Tae Kim
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7883 , G11C16/0441 , H01L29/40114 , H01L29/42328 , H01L29/66825
摘要： A nonvolatile memory (NVM) device includes a floating gate on a semiconductor substrate and a gate insulating layer between the semiconductor substrate and the floating gate. A tunnel insulating layer is disposed between the semiconductor substrate and the floating gate. The tunnel insulating layer is thinner than the gate insulating layer. A first inter-gate insulating layer is disposed on the floating gate, and a sensing gate is disposed on the first inter-gate insulating layer. The sensing gate covers a first portion of the floating gate. A control gate is disposed to cover a top surface and a sidewall of a second portion of the floating gate. A second inter-gate insulating layer is disposed between the control gate and the sensing gate and between the control gate and the floating gate. Operation methods and fabrication methods of the NVM device are also provided.
摘要翻译：非易失性存储器（NVM）器件包括半导体衬底上的浮置栅极和半导体衬底与浮置栅极之间的栅极绝缘层。隧道绝缘层设置在半导体衬底和浮动栅极之间。隧道绝缘层比栅极绝缘层薄。第一栅极间绝缘层设置在浮置栅极上，感测栅极设置在第一栅极间绝缘层上。感测门覆盖浮动栅极的第一部分。控制门设置成覆盖浮动栅极的第二部分的顶表面和侧壁。第二栅极间绝缘层设置在控制栅极和感测栅极之间以及控制栅极和浮动栅极之间。还提供了NVM设备的操作方法和制造方法。

20. 发明申请

US20060170031A1 Semiconductor device having transistor with vertical gate electrode and method of fabricating the same 失效
公开(公告)号：US20060170031A1
公开(公告)日：2006-08-03
申请号：US11344560
申请日：2006-01-31
申请人： Sang-Woo Kang , Jeong-Uk Han , Yong-Tae Kim , Seung-Beom Yoon
发明人： Sang-Woo Kang , Jeong-Uk Han , Yong-Tae Kim , Seung-Beom Yoon
IPC分类号： H01L29/788
CPC分类号： H01L29/785 , H01L27/105 , H01L27/115 , H01L27/228 , H01L27/2436 , H01L29/7881 , H01L29/792
摘要： A semiconductor device includes transistors with a vertical gate electrode. In a transistor structure, a semiconductor pattern has first and second sides facing in a transverse direction, and third and fourth sides facing in a longitudinal direction. Gate patterns are disposed adjacent to the first and second sides of the semiconductor pattern. Impurity patterns directly contact the third and fourth sides of the semiconductor pattern. A gate insulating pattern is interposed between the gate patterns and the semiconductor pattern.

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