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11. 发明申请

US20050278551A1 METHOD FOR SYSTEM LEVEL PROTECTION OF FIELD PROGRAMMABLE LOGIC DEVICES 失效
标题翻译：用于系统级保护现场可编程逻辑器件的方法
公开(公告)号：US20050278551A1
公开(公告)日：2005-12-15
申请号：US10709809
申请日：2004-05-28
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds
IPC分类号： G06F21/00 , H04L9/32
CPC分类号： G06F21/76
摘要： A method for protecting a dynamically reconfigurable computing system includes generating an encoding signature and passing the encoding signature, through a system level bus, to at least one field programmable logic device and to a function library included within the system. The function library contains a plurality of functions for selective programming into the at least one field programmable logic device. A lock is generated so as to prevent external resources with respect to the system from accessing the encoding signature during the passing thereof.
摘要翻译：一种用于保护动态可重新配置的计算系统的方法包括生成编码签名并将编码签名通过系统级总线传递到至少一个现场可编程逻辑设备和包括在该系统内的功能库。功能库包含用于对至少一个现场可编程逻辑器件进行选择性编程的多个功能。生成锁，以防止相对于系统的外部资源在通过期间访问编码签名。

12. 发明申请

US20070278582A1 STRUCTURE AND METHOD FOR IMPLEMENTING OXIDE LEAKAGE BASED VOLTAGE DIVIDER NETWORK FOR INTEGRATED CIRCUIT DEVICES 审中-公开
公开(公告)号：US20070278582A1
公开(公告)日：2007-12-06
申请号：US11841247
申请日：2007-08-20
申请人： Kenneth Goodnow , Joseph Iadanza , Edward Nowak , Douglas Stout
发明人： Kenneth Goodnow , Joseph Iadanza , Edward Nowak , Douglas Stout
IPC分类号： H01L29/739
CPC分类号： H01L29/42384 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/785 , H01L29/78645 , H01L29/78648
摘要： A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.

13. 发明申请

US20070252641A1 STRUCTURE AND METHOD FOR IMPLEMENTING OXIDE LEAKAGE BASED VOLTAGE DIVIDER NETWORK FOR INTEGRATED CIRCUIT DEVICES 有权
标题翻译：用于集成电路设备实现基于氧化物泄漏的电压分压网络的结构和方法
公开(公告)号：US20070252641A1
公开(公告)日：2007-11-01
申请号：US11380799
申请日：2006-04-28
申请人： Kenneth Goodnow , Joseph Iadanza , Edward Nowak , Douglas Stout
发明人： Kenneth Goodnow , Joseph Iadanza , Edward Nowak , Douglas Stout
IPC分类号： G05F1/10
CPC分类号： H01L29/42384 , H01L21/823842 , H01L21/823857 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/785 , H01L29/78645 , H01L29/78648
摘要： A voltage divider device includes a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region. An input voltage is coupled between the first and second gates, and an output voltage is taken from at least one of a source of the FET and a drain of the FET, wherein the output voltage represents a divided voltage with respect to the input voltage.
摘要翻译：分压器件包括具有第一栅极的双栅极场效应晶体管（FET）和设置在主体区域的相对侧的第二栅极。输入电压耦合在第一和第二栅极之间，并且输出电压取自FET的源极和FET的漏极中的至少一个，其中输出电压表示相对于输入电压的分压。

14. 发明申请

US20050251778A1 System and method for dynamically executing a function in a programmable logic array 有权
标题翻译：用于在可编程逻辑阵列中动态执行功能的系统和方法
公开(公告)号：US20050251778A1
公开(公告)日：2005-11-10
申请号：US11181053
申请日：2005-07-14
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Jack Smith , Sebastian Ventrone
IPC分类号： G06F15/78 , H03K19/177 , H03K19/00
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17756 , H03K19/1776
摘要： A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB 1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.
摘要翻译：一种可重构逻辑阵列（RLA）系统（104），包括RLA（108）和编程器（112），用于循环地重新编程RLA。需要比RLA中包含的逻辑大的功能（F）被划分为多个功能块（FB 1，FB 2，FB 3）。程序员包含将RLA分割成位于两个存储区域SR 1，SR 2之间的功能区域FR的软件（144）。然后，程序员用功能块的功能块顺序地对功能区进行编程，使得功能块在存储区之间交替地进行处理。当编程器用下一个功能块重新配置功能区域并且重新配置存储区域之一以接收下一个功能块的输出时，从当前功能块传递到下一个功能块的数据被保存在另一个存储区域中。

15. 发明申请

US20050125680A1 MULTIPROCESSOR CODE FIX USING A LOCAL CACHE 有权
标题翻译：使用本地缓存的多处理器代码固定
公开(公告)号：US20050125680A1
公开(公告)日：2005-06-09
申请号：US10707304
申请日：2003-12-04
申请人： Kenneth Goodnow , Riyon Harding
发明人： Kenneth Goodnow , Riyon Harding
IPC分类号： H04L9/32
CPC分类号： G06F8/65
摘要： Operating code fixes are supplied to multiple processors utilizing the same operating code by storing the correction code fixes in a central RAM, and distributing the code fixes over a dedicated code fix bus to a local cache for each processor. The first processor encountering a code fix requests the code fix from the RAM, which then distributes the code fix over the code fix bus to all of the local caches which are automatically updated with the new code. The system is particularly applicable to an integrated circuit having multiple processors fabricated on a chip, wherein the RAM is on-chip and is connected to an off-chip EEPROM that loads corrected code fixes to the on-chip RAM at power-up.
摘要翻译：通过将修正代码修正存储在中央RAM中并将专用代码修复总线上的代码修正分配给每个处理器的本地高速缓存，将操作代码修复程序提供给使用相同操作代码的多个处理器。遇到代码修复的第一个处理器从RAM请求代码修复，然后将代码修复总线分配给所有使用新代码自动更新的本地缓存。该系统特别适用于具有在芯片上制造的多个处理器的集成电路，其中RAM是芯片上的，并且连接到片外EEPROM，其在加电时将校正的代码固定件加载到片上RAM。

16. 发明申请

US20080024197A1 METHOD AND ARCHITECTURE FOR POWER MANAGEMENT OF AN ELECTRONIC DEVICE 有权
标题翻译：电子设备电源管理的方法和架构
公开(公告)号：US20080024197A1
公开(公告)日：2008-01-31
申请号：US11846578
申请日：2007-08-29
申请人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Keith Williams , Sebastian Ventrone
发明人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Keith Williams , Sebastian Ventrone
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , G06F1/3287 , H01L25/16 , H01L28/60 , H01L2224/16225 , H01L2924/00011 , H01L2924/00014 , H01L2924/19105 , Y02D10/171 , H01L2224/0401
摘要： A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.
摘要翻译：一种降低低功率电子设备中的静态功耗的方法。所述电子设备包括一个或多个功率岛，每个功率岛包括：将本地电网耦合到本地接地网的局部存储电容器; 以及连接在本地电网与本地接地网之间的功能电路; 将全球电网耦合到全球接地网的全球存储电容器，每个局部地电网连接到全球接地网; 一个或多个开关，每个开关选择性地将全局电网连接到单个和不同的对应的局部电网; 以及适于打开和关闭所述一个或多个开关的电力调度单元。

17. 发明申请

US20070242507A1 DETERMINING HISTORY STATE OF DATA IN DATA RETAINING DEVICE BASED ON STATE OF PARTIALLY DEPLETED SILICON-ON-INSULATOR 失效
标题翻译：根据部分绝缘硅绝缘体的状态确定数据保留装置中数据的历史状态
公开(公告)号：US20070242507A1
公开(公告)日：2007-10-18
申请号：US11279507
申请日：2006-04-12
申请人： Kerry Bernstein , Kenneth Goodnow , Clearence Ogilvis , Sebastian Ventrone , Kelth Williams
发明人： Kerry Bernstein , Kenneth Goodnow , Clearence Ogilvis , Sebastian Ventrone , Kelth Williams
IPC分类号： G11C11/34
CPC分类号： G11C11/417
摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.
摘要翻译：公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。

18. 发明申请

US20070198808A1 PROCESSOR PIPELINE ARCHITECTURE LOGIC STATE RETENTION SYSTEMS AND METHODS 有权
标题翻译：处理器管道结构逻辑状态保持系统和方法
公开(公告)号：US20070198808A1
公开(公告)日：2007-08-23
申请号：US11276236
申请日：2006-02-20
申请人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Keith Williams
发明人： Kerry Bernstein , Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Keith Williams
IPC分类号： G06F15/00
CPC分类号： G06F9/3869 , G11C27/026
摘要： A system, method and program product for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译：公开了一种用于保持处理器流水线架构的逻辑状态的系统，方法和程序产品。比较器位于处理器流水线架构的两个阶段之间。存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。提供了与早期输出值相同的参考逻辑。逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点处产生逻辑，该逻辑是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态电容器。提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

19. 发明申请

US20070162792A1 METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES 失效
标题翻译：增加可编程逻辑器件制造工艺的方法
公开(公告)号：US20070162792A1
公开(公告)日：2007-07-12
申请号：US11275536
申请日：2006-01-12
申请人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Paul Zuchowski
发明人： Kenneth Goodnow , Clarence Ogilvie , Christopher Reynolds , Sebastian Ventrone , Paul Zuchowski
IPC分类号： G01R31/26 , G11C29/00
CPC分类号： G01R31/31718 , G11C17/14 , G11C29/88 , H03K19/17764 , H03K19/17796
摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.
摘要翻译：一种提高现场可编程门阵列（FPGAS）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

20. 发明申请

US20060190744A1 METHOD OF SWITCHING VOLTAGE ISLANDS IN INTEGRATED CIRCUITS 有权
标题翻译：在电路中切换电压岛的方法
公开(公告)号：US20060190744A1
公开(公告)日：2006-08-24
申请号：US10906476
申请日：2005-02-22
申请人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
发明人： Rafael Blanco , John Cohn , Kenneth Goodnow , Douglas Stout , Sebastian Ventrone
IPC分类号： G06F1/26
CPC分类号： G06F1/3287 , G06F1/26 , G06F1/3203 , Y02D10/171
摘要： An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (such as a voltage island) to be switched on to or off the power grid.
摘要翻译：集成电路具有电网和一组可独立切换的电压岛，以及用于测量电网电压和历史的系统和方法，以确定允许大容性负载（例如，电压岛）被接通或断开电网。

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