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11. 再颁专利

USRE35294E Polysilicon encapsulated localized oxidation of silicon 失效
标题翻译：多晶硅封装了硅的局部氧化
公开(公告)号：USRE35294E
公开(公告)日：1996-07-09
申请号：US245131
申请日：1994-05-17
申请人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth , Wayne J. Ray
发明人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth , Wayne J. Ray
IPC分类号： H01L21/32 , H01L21/762 , H01L21/76
CPC分类号： H01L21/76202 , H01L21/32 , Y10S148/117
摘要： A reduction in defects and lateral encroachment is obtained by .[.utilizing a high pressure oxidation in conjunction with.]. an oxidizable layer conformally deposited over an oxidation mask. .[.The.]. .Iadd.In one embodiment, the .Iaddend.use of high pressure oxidation provides for the formation of LOCOS oxide without the formation of defects. Any native oxide present on the substrate surface is removed by using a ramped temperature deposition process to form oxidizable layer and/or a high temperature anneal is performed to remove the native oxide at the substrate surface. In this embodiment, any oxide which can act as a pipe for oxygen diffusion is removed. Therefore, nominal or no lateral encroachment is exhibited..Iadd.Alternately, lateral encroachment can be controlled by intentionally growing an oxide layer on the substrate surface. .Iaddend.
摘要翻译：缺陷和横向侵蚀的减少通过[利用高压氧化与]氧化掩膜上共形沉积的可氧化层来获得。在一个实施方案中，使用高压氧化提供形成LOCOS氧化物而不形成缺陷。存在于衬底表面上的任何天然氧化物通过使用斜变温度沉积工艺以形成可氧化层而被去除，和/或进行高温退火以去除衬底表面处的自然氧化物。在本实施例中，可以除去可充当氧扩散管的任何氧化物。因此，表现为名义上或没有横向侵占。或者，可以通过在衬底表面上有意地生长氧化物层来控制横向侵蚀。

12. 发明授权

US08824114B2 Monitor circuit for determining the lifetime of a semiconductor device 有权
标题翻译：用于确定半导体器件的寿命的监视器电路
公开(公告)号：US08824114B2
公开(公告)日：2014-09-02
申请号：US12764689
申请日：2010-04-21
申请人： Jason C. Perkey , Scott S. Roth , Tim J. Zoerner
发明人： Jason C. Perkey , Scott S. Roth , Tim J. Zoerner
IPC分类号： H02H3/00 , G01R31/26 , H02H3/22 , H02H9/00 , H01L21/768
CPC分类号： G01R31/2642
摘要： A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor is positioned a first predetermined distance from the first conductor. The first detect and disconnect circuit has a first terminal coupled to the second conductor and a second terminal coupled to a second power supply voltage terminal. The first detect and disconnect circuit detects a first electrical property change between the second conductor and the first conductor. In response to detecting the change in the first electrical property, the second conductor is disconnected from the second power supply voltage terminal. A method for manufacturing a semiconductor device comprising the circuit is also provided.
摘要翻译：电路包括第一导体，第二导体和第一检测和断开电路。第一导体耦合到第一电源电压端子。第二导体位于距第一导体第一预定距离处。第一检测和断开电路具有耦合到第二导体的第一端子和耦合到第二电源电压端子的第二端子。第一检测和断开电路检测第二导体和第一导体之间的第一电特性变化。响应于检测到第一电气特性的变化，第二导体与第二电源电压端子断开。还提供了一种制造包括该电路的半导体器件的方法。

13. 发明授权

US5814868A Transistor having an offset channel section 失效
标题翻译：晶体管具有偏移通道部分
公开(公告)号：US5814868A
公开(公告)日：1998-09-29
申请号：US298965
申请日：1994-09-02
申请人： Scott S. Roth , William C. McFadden , Alexander J. Pepe
发明人： Scott S. Roth , William C. McFadden , Alexander J. Pepe
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/45 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/78696 , H01L27/11 , H01L27/1108 , H01L29/458 , H01L29/78624 , Y10S148/15
摘要： The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.
摘要翻译：本发明包括具有第一和第二部分的沟道区的晶体管，其中所述部分具有大致垂直于彼此的长度。防止发明还包括SRAM单元中的晶体管和用于形成晶体管和SRAM单元的处理。在所描述的实施例中，第一部分具有大致垂直的长度，并且第二部分具有通常沿横向方向延伸的长度。第一部分可以是硅插头的未掺杂或轻掺杂的部分。插塞可以形成包括蚀刻或抛光步骤。

14. 发明授权

US5604159A Method of making a contact structure 失效
标题翻译：制作接触结构的方法
公开(公告)号：US5604159A
公开(公告)日：1997-02-18
申请号：US188986
申请日：1994-01-31
申请人： Kent J. Cooper , Scott S. Roth
发明人： Kent J. Cooper , Scott S. Roth
IPC分类号： H01L21/28 , H01L21/44 , H01L21/48
CPC分类号： H01L21/28
摘要： The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.
摘要翻译：在通过沟槽隔离制造的集成电路中接触半导体器件所需的水平表面积被最小化，而不会通过利用沟槽侧壁的垂直表面积来降低接触电阻。沟槽隔离区（40）形成在半导体衬底（12）内。然后形成掺杂区域（74,96），使得其邻接沟槽侧壁（24）。然后，通过在沟槽隔离区域（40）内形成凹部（55,112）来暴露沟槽侧壁（24）的与掺杂区域（74,96）邻接的部分（56,110）。然后形成导电构件（66,114,118），使得其沿着暴露的沟槽侧壁以及沿着半导体衬底（12）的主表面（13）电耦合到掺杂区域（74,96）），并且导致形成低电阻接触结构。

15. 发明授权

US5583360A Vertically formed neuron transister having a floating gate and a control gate 失效
标题翻译：具有浮动栅极和控制栅极的垂直形成的神经元转运器
公开(公告)号：US5583360A
公开(公告)日：1996-12-10
申请号：US520363
申请日：1995-08-28
申请人： Scott S. Roth , William C. McFadden , Alexander J. Pepe
发明人： Scott S. Roth , William C. McFadden , Alexander J. Pepe
IPC分类号： H01L21/8247 , H01L27/115 , H01L27/108 , H01L29/76 , H01L29/788
CPC分类号： H01L27/11517 , H01L27/115 , Y10S438/972
摘要： A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.
摘要翻译：通过提供衬底（12）开始形成垂直神经元MOSFET的方法。在衬底（12）上形成一个或多个导电层（24和28）。通过导电层（24和28）的一部分形成开口（32），以从导电层（24和28）形成一个或多个控制电极。在每个控制电极附近形成浮动栅极（36和38）。在开口（32）内并且在控制电极和浮动栅极（36和38）之间形成电介质层（34），以提供控制电极和浮动栅极（36和38）之间的电容耦合。可以通过各向同性侧壁蚀刻和其它方法来改变每个控制电极的电容耦合。通过以垂直方式形成神经元MOSFET，与已知的神经元MOSFET结构相比，神经元MOSFET的表面积减小。

16. 发明授权

US5480820A Method of making a vertically formed neuron transistor having a floating gate and a control gate and a method of formation 失效
标题翻译：制造具有浮动栅极和控制栅极的垂直形成的神经元晶体管的方法和形成方法
公开(公告)号：US5480820A
公开(公告)日：1996-01-02
申请号：US425267
申请日：1995-04-17
申请人： Scott S. Roth , William C. McFadden , Alexander J. Pepe
发明人： Scott S. Roth , William C. McFadden , Alexander J. Pepe
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11517 , H01L27/115 , Y10S438/972
摘要： A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.
摘要翻译：通过提供衬底（12）开始形成垂直神经元MOSFET的方法。在衬底（12）上形成一个或多个导电层（24和28）。通过导电层（24和28）的一部分形成开口（32），以从导电层（24和28）形成一个或多个控制电极。在每个控制电极附近形成浮动栅极（36和38）。在开口（32）内并且在控制电极和浮动栅极（36和38）之间形成电介质层（34），以提供控制电极和浮动栅极（36和38）之间的电容耦合。可以通过各向同性侧壁蚀刻和其它方法来改变每个控制电极的电容耦合。通过以垂直方式形成神经元MOSFET，与已知的神经元MOSFET结构相比，神经元MOSFET的表面积减小。

17. 发明授权

US4662956A Method for prevention of autodoping of epitaxial layers 失效
标题翻译：防止外延层自掺杂的方法
公开(公告)号：US4662956A
公开(公告)日：1987-05-05
申请号：US718758
申请日：1985-04-01
申请人： Scott S. Roth , Joe Steinberg , H. Scott Morgan
发明人： Scott S. Roth , Joe Steinberg , H. Scott Morgan
IPC分类号： H01L21/205 , H01L21/20 , H01L21/22 , H01L21/306
CPC分类号： H01L21/2205 , H01L21/02381 , H01L21/02546 , H01L21/02658 , Y10S148/007 , Y10S438/916
摘要： A method for the prevention of dopant diffusion from the back side of a doped semiconductor substrate during epitaxial layer growth. The entire surface of the substrate is first covered with a cleanly etchable material. Around the entire first layer is formed a second dopant diffusion barrier layer. The front sides of the layers are then selectively etched away to expose the front side of the substrate upon which the epitaxial layer will be grown without contamination of dopant diffusion from the sealed back side of the substrate.
摘要翻译：一种用于在外延层生长期间防止掺杂半导体衬底的背面掺杂剂扩散的方法。首先用干净的可蚀刻材料覆盖基底的整个表面。在整个第一层周围形成第二掺杂剂扩散阻挡层。然后选择性地蚀刻掉这些层的前侧以暴露衬底的正面，在衬底的前侧将外延层生长而不会从衬底的密封背面污染掺杂剂扩散。

18. 发明申请

US20070275539A1 METHOD OF STIMULATING DIE CIRCUITRY AND STRUCTURE THEREFOR 有权
标题翻译：刺激电路和其结构的方法
公开(公告)号：US20070275539A1
公开(公告)日：2007-11-29
申请号：US11420551
申请日：2006-05-26
申请人： Mohammed K. Rashid , Mahbub M. Rashed , Scott S. Roth
发明人： Mohammed K. Rashid , Mahbub M. Rashed , Scott S. Roth
IPC分类号： H01L21/00
CPC分类号： G01R31/2884 , G01R31/2831 , H01L22/32 , H01L2224/02166 , H01L2224/05554
摘要： A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further includes accessing the scribe grid pad to stimulate the die circuitry. A wafer includes a first die. The first die includes die circuitry, a plurality of conductive layers, and a bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality of conductive layers. The wafer includes a scribe grid having a scribe grid pad, and an interconnect electrically connecting the scribe grid pad to the die circuitry. The plurality of die of the wafer can then be singulated, and at least one of the singulated die can be packaged.
摘要翻译：一种方法包括提供具有第一管芯和划线栅格的晶片，其中第一管芯具有管芯电路和电连接到管芯电路的接合焊盘，并且其中划线栅具有电连接到管芯电路的划线栅焊盘。该方法还包括访问划线网格焊盘以刺激管芯电路。晶片包括第一模具。第一裸片包括晶片电路，多个导电层以及通过多个导电层中的至少一个导电层电连接到管芯电路的焊盘。晶片包括具有划线网格焊盘的划线网格，以及将划线网格焊盘与管芯电路电连接的互连。然后可以对晶片的多个裸片进行单片化，并且可以封装单个模具中的至少一个。

19. 发明授权

US06285073B1 Contact structure and method of formation 失效
标题翻译：接触结构和形成方法
公开(公告)号：US06285073B1
公开(公告)日：2001-09-04
申请号：US08453689
申请日：1995-05-30
申请人： Kent J. Cooper , Scott S. Roth
发明人： Kent J. Cooper , Scott S. Roth
IPC分类号： H01L2906
CPC分类号： H01L21/28
摘要： The horizontal surface area required to contact semiconductor devices, in integrated circuits fabricated with trench isolation, is minimized without degrading contact resistance by utilizing the vertical surface area of the trench sidewall. A trench isolation region (40) is formed within the semiconductor substrate (12). A doped region (74, 96) is then formed such that it abuts the trench sidewall (24). A portion (56, 110) of the trench sidewall (24), abutting the doped region (74, 96), is then exposed by forming a recess (55, 112) within the trench isolation region (40). A conductive member (66, 114, 118) is then formed such that it is electrically coupled to the doped region (74, 96) along the exposed trench sidewall, as well as along the major surface (13) of the semiconductor substrate (12), and results in the formation of a low resistance contact structure.
摘要翻译：在通过沟槽隔离制造的集成电路中接触半导体器件所需的水平表面积被最小化，而不会通过利用沟槽侧壁的垂直表面积来降低接触电阻。沟槽隔离区（40）形成在半导体衬底（12）内。然后形成掺杂区域（74,96），使得其邻接沟槽侧壁（24）。然后，通过在沟槽隔离区域（40）内形成凹部（55,112）来暴露沟槽侧壁（24）的与掺杂区域（74,96）邻接的部分（56,110）。然后形成导电构件（66,114,118），使得其沿着暴露的沟槽侧壁以及沿着半导体衬底（12）的主表面（13）电耦合到掺杂区域（74,96）），并且导致形成低电阻接触结构。

20. 发明授权

US5219793A Method for forming pitch independent contacts and a semiconductor device having the same 失效
标题翻译：用于形成俯仰独立触点的方法和具有该触点的半导体器件
公开(公告)号：US5219793A
公开(公告)日：1993-06-15
申请号：US709554
申请日：1991-06-03
申请人： Kent J. Cooper , Jung-Hui Lin , Scott S. Roth , Bernard J. Roman , Carlos A. Mazure , Bich-Yen Nguyen , Wayne J. Ray
发明人： Kent J. Cooper , Jung-Hui Lin , Scott S. Roth , Bernard J. Roman , Carlos A. Mazure , Bich-Yen Nguyen , Wayne J. Ray
IPC分类号： H01L21/60
CPC分类号： H01L21/76897 , Y10S148/02 , Y10S438/97
摘要： A contact is formed in a semiconductor device (10), independent of underlying topography or pitch. In one method of the present invention, an insulating layer (18) is deposited over a semiconductor substrate (12). An etch stop layer (20) is deposited over the insulating layer. A frame structure (22) is formed on the etch stop material and defines at least one contact region (23 and/or 25) within which the etch stop material is exposed. The exposed portions of the etch stop material are removed from the contact region to expose a portion of the insulating layer. The exposed portion of the insulating layer is then anisotropically etched and at least one contact (30 and/or 32) is formed in the contact region. Depending on where the contact region is positioned, either a self-aligned contact or a non-self-aligned contact may be formed, or both types of contacts may be formed simultaneously.
摘要翻译：接触形成在半导体器件（10）中，与底层的形貌或间距无关。在本发明的一种方法中，绝缘层（18）沉积在半导体衬底（12）上。在绝缘层上沉积蚀刻停止层（20）。在所述蚀刻停止材料上形成框架结构（22），并且限定了在所述蚀刻停止材料暴露的至少一个接触区域（23和/或25）。从接触区域去除蚀刻停止材料的暴露部分以暴露绝缘层的一部分。绝缘层的暴露部分然后被各向异性蚀刻，并且在接触区域中形成至少一个触点（30和/或32）。取决于接触区域的位置，可以形成自对准接触或非自对准接触，或者可以同时形成两种类型的接触。

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