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11. 发明授权

US09257520B2 Semiconductor devices including a stressor in a recess and methods of forming the same 有权
公开(公告)号：US09257520B2
公开(公告)日：2016-02-09
申请号：US14680349
申请日：2015-04-07
申请人： Dong-Suk Shin , Hyun-Chul Kang , Dong-Hyun Roh , Pan-Kwi Park , Geo-Myung Shin , Nae-In Lee , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim
发明人： Dong-Suk Shin , Hyun-Chul Kang , Dong-Hyun Roh , Pan-Kwi Park , Geo-Myung Shin , Nae-In Lee , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim
IPC分类号： H01L29/49 , H01L29/78 , H01L21/8234 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823425 , H01L27/0207 , H01L27/088 , H01L29/0847 , H01L29/1095 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/4966 , H01L29/66492 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7836
摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

12. 发明授权

US09129952B2 Semiconductor devices including a stressor in a recess and methods of forming the same 有权
标题翻译：包括凹部中的应力器的半导体器件及其形成方法
公开(公告)号：US09129952B2
公开(公告)日：2015-09-08
申请号：US14033718
申请日：2013-09-23
申请人： Dong-Suk Shin , Hyun-Chul Kang , Dong-Hyun Roh , Pan-Kwi Park , Geo-Myung Shin , Nae-In Lee , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim
发明人： Dong-Suk Shin , Hyun-Chul Kang , Dong-Hyun Roh , Pan-Kwi Park , Geo-Myung Shin , Nae-In Lee , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim
IPC分类号： H01L29/78 , H01L29/49 , H01L21/8234 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823425 , H01L27/0207 , H01L27/088 , H01L29/0847 , H01L29/1095 , H01L29/161 , H01L29/165 , H01L29/167 , H01L29/4966 , H01L29/66492 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7833 , H01L29/7836
摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
摘要翻译：提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。所述方法还可以包括在沟槽中形成嵌入的应力源。嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。

13. 发明授权

US09024385B2 Semiconductor devices including a stressor in a recess and methods of forming the same 有权
公开(公告)号：US09024385B2
公开(公告)日：2015-05-05
申请号：US14033718
申请日：2013-09-23
申请人： Dong-Suk Shin , Hyun-Chul Kang , Dong-Hyun Roh , Pan-Kwi Park , Geo-Myung Shin , Nae-In Lee , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim
发明人： Dong-Suk Shin , Hyun-Chul Kang , Dong-Hyun Roh , Pan-Kwi Park , Geo-Myung Shin , Nae-In Lee , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim
IPC分类号： H01L29/78 , H01L29/49 , H01L21/8234 , H01L29/66
摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

14. 发明授权

US07902019B2 Dielectric layer for semiconductor device and method of manufacturing the same 有权
标题翻译：用于半导体器件的介电层及其制造方法
公开(公告)号：US07902019B2
公开(公告)日：2011-03-08
申请号：US12098373
申请日：2008-04-04
申请人： Jong-Ho Lee , Nae-In Lee
发明人： Jong-Ho Lee , Nae-In Lee
IPC分类号： H01L21/8249
CPC分类号： H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02192 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L28/56 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7881 , H01L29/94
摘要： A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.
摘要翻译：半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。高k电介质层包括金属合金氧化物。

15. 发明申请

US20100136790A1 Method of fabricating semiconductor integrated circuit device 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20100136790A1
公开(公告)日：2010-06-03
申请号：US12591534
申请日：2009-11-23
申请人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
发明人： Chong-Kwang Chang , Hong-Jae Shin , Nae-In Lee , Kwang-Hyeon Baik , Seung-Il Bok , Hyo-Jeong Kim
IPC分类号： H01L21/302
CPC分类号： H01L21/0337
摘要： A method of fabricating a semiconductor integrated circuit device, including providing a semiconductor substrate, sequentially forming an etching target layer and a hard mask layer on the semiconductor substrate, forming first etch masks on the hard mask layer, the first etch masks including a plurality of first line patterns spaced apart from one another at a first pitch and extending in a first direction, forming first hard mask patterns by etching the hard mask layer using the first etch masks, forming second etch masks on the first hard mask patterns, the second etch masks including a plurality of second line patterns spaced apart from one another at a second pitch and extending in a second direction different from the first direction, forming second hard mask patterns by etching the first hard mask patterns using the second etch masks, forming spacers on sidewalls of the second hard mask patterns, and patterning the etching target layer using the second hard mask patterns having the spacers.
摘要翻译：一种制造半导体集成电路器件的方法，包括提供半导体衬底，在半导体衬底上依次形成蚀刻目标层和硬掩模层，在硬掩模层上形成第一蚀刻掩模，第一蚀刻掩模包括多个第一线图案以第一间距彼此间隔开并且沿第一方向延伸，通过使用第一蚀刻掩模蚀刻硬掩模层形成第一硬掩模图案，在第一硬掩模图案上形成第二蚀刻掩模，第二蚀刻掩模，包括以第二间距彼此间隔开并且沿与第一方向不同的第二方向延伸的多个第二线图案，通过使用第二蚀刻掩模蚀刻第一硬掩模图案形成第二硬掩模图案，在第第二硬掩模图案的侧壁，以及使用具有t的第二硬掩模图案来图案化蚀刻目标层他的间隔。

16. 发明授权

US06998309B2 Method of manufacturing a non-volatile semiconductor memory device 有权
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US06998309B2
公开(公告)日：2006-02-14
申请号：US10786239
申请日：2004-02-24
申请人： In-Wook Cho , Nae-In Lee , Kwang-Wook Koh , Geum-Jong Bae , Sang-Su Kim , Jin-Hee Kim , Sung-Ho Kim , Ki-Chul Kim
发明人： In-Wook Cho , Nae-In Lee , Kwang-Wook Koh , Geum-Jong Bae , Sang-Su Kim , Jin-Hee Kim , Sung-Ho Kim , Ki-Chul Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568 , Y10S438/954
摘要： A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.
摘要翻译：制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。在包括在电介质层图案上的衬底上形成多晶硅层。图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

17. 发明授权

US06917085B2 Semiconductor transistor using L-shaped spacer 有权
标题翻译：半导体晶体管采用L型间隔器
公开(公告)号：US06917085B2
公开(公告)日：2005-07-12
申请号：US10728811
申请日：2003-12-08
申请人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Young-Gun Ko , Tae-Hee Choe , Sang-Su Kim
发明人： Geum-Jong Bae , Nae-In Lee , Hwa-Sung Rhee , Young-Gun Ko , Tae-Hee Choe , Sang-Su Kim
IPC分类号： H01L21/336 , H01L29/78 , H01L29/76
CPC分类号： H01L29/66598 , H01L29/66507 , H01L29/66515 , H01L29/6653 , H01L29/6656 , H01L29/6659
摘要： The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.
摘要翻译：本发明提供一种使用L形间隔物的半导体晶体管。半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三间隔物。在第三间隔物和栅极图案之间以及在第三间隔物和基底之间形成L形的第四间隔物。高浓度接合区域位于第三间隔物之外的基板中，并且低浓度接合区域位于第三间隔物的水平突出部分的下方。中等浓度接合区域位于高浓度和低浓度接合区域之间。

18. 发明授权

US06524902B2 Method of manufacturing CMOS semiconductor device 失效
标题翻译：制造CMOS半导体器件的方法
公开(公告)号：US06524902B2
公开(公告)日：2003-02-25
申请号：US10001619
申请日：2001-10-23
申请人： Hwa-Sung Rhee , Geum-Jong Bae , Tae-Hee Choe , Sang-Su Kim , Nae-In Lee
发明人： Hwa-Sung Rhee , Geum-Jong Bae , Tae-Hee Choe , Sang-Su Kim , Nae-In Lee
IPC分类号： H01L218238
CPC分类号： H01L21/2807 , H01L21/823842
摘要： In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.
摘要翻译：在具有衬底的CMOS半导体器件中，形成在衬底上的栅极绝缘层，至少一个在至少一个PMOS晶体管区域中的衬底上形成的第一多晶硅栅极和至少一个第二多晶硅栅极，至少形成在衬底上至少一个一个NMOS晶体管区域，第一多晶硅栅极中的Ge的总量与第二多晶硅栅极中的Ge的总量相同，第一和/或第二多晶硅栅极中的Ge浓度的分布根据与栅极绝缘的距离而不同与栅极绝缘层相邻的第一多晶硅栅极的一部分中的Ge层浓度高于第二多晶硅栅极中的Ge浓度。与栅极绝缘层相邻的第一多晶硅栅极部分的Ge浓度比第二多晶硅栅极中的Ge浓度高两倍。例如，与栅极绝缘层相邻的第一多晶硅栅极的Ge浓度优选大于20％，与栅极绝缘层相邻的第二多晶硅栅极的部分Ge浓度低于10 ％。

19. 发明授权

US09214530B2 Methods of forming semiconductor devices including a stressor in a recess 有权
标题翻译：在凹部中形成包括应力源的半导体器件的方法
公开(公告)号：US09214530B2
公开(公告)日：2015-12-15
申请号：US14033639
申请日：2013-09-23
申请人： Dong-Suk Shin , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim , Nae-In Lee
发明人： Dong-Suk Shin , Chul-Woong Lee , Hoi-Sung Chung , Young-Tak Kim , Nae-In Lee
IPC分类号： H01L21/336 , H01L29/66 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/04 , H01L29/06
CPC分类号： H01L29/7848 , H01L21/02636 , H01L21/30604 , H01L21/823412 , H01L21/823425 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/088 , H01L29/045 , H01L29/0603 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/66545 , H01L29/6656 , H01L29/66568 , H01L29/66575 , H01L29/66636 , H01L29/7833 , H01L29/7834
摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
摘要翻译：提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。所述方法可以包括在有源区中形成包含磷的快速蚀刻区域，并且通过使快速蚀刻区域凹陷来在有源区中形成第一沟槽。所述方法还可以包括通过使用定向蚀刻工艺扩大第一沟槽并在第二沟槽中形成应力源来在有源区域中形成第二沟槽。第二沟槽可以包括有源区的切口部分。

20. 发明申请

US20130320434A1 SEMICONDUCTOR DEVICE HAVING EMBEDDED STRAIN-INDUCING PATTERN AND METHOD OF FORMING THE SAME 有权
标题翻译：具有嵌入式应变诱导图案的半导体器件及其形成方法
公开(公告)号：US20130320434A1
公开(公告)日：2013-12-05
申请号：US13908440
申请日：2013-06-03
申请人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
发明人： Dong-Suk Shin , Myung-Sun Kim , Seong-Jin Nam , Pan-Kwi Park , Hoi-Sung Chung , Nae-In Lee
IPC分类号： H01L29/78
CPC分类号： H01L27/1104 , H01L21/02532 , H01L21/02636 , H01L21/28247 , H01L21/30604 , H01L21/823807 , H01L21/823814 , H01L27/088 , H01L27/1116 , H01L29/0847 , H01L29/1083 , H01L29/16 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/513 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/6659 , H01L29/66636 , H01L29/7827 , H01L29/7833 , H01L29/7834 , H01L29/7845 , H01L29/7848 , H01L29/785 , H01L29/78696
摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.
摘要翻译：在半导体器件中，第一有源区具有第一西格玛形状，第二有源区具有第二西格玛形状。当垂直于衬底并将第一栅电极的侧表面通过第一区域的线被定义为第一垂直线时，当垂直于衬底并通过第二栅电极的侧表面的线在第二区域被定义为第二垂直线时，当第一垂直线和第一沟槽之间的最短距离被定义为第一水平距离时，并且当第二垂直线和第二沟槽之间的最短距离被定义为第二水平距离，第一水平距离和第二水平距离之间的差等于或小于1nm。

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