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11. 发明授权

US09257191B1 Charge redistribution during erase in charge trapping memory 有权
公开(公告)号：US09257191B1
公开(公告)日：2016-02-09
申请号：US14472889
申请日：2014-08-29
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Ching-Huang Lu , Yingda Dong
IPC分类号： G11C16/04 , G11C16/14 , G11C16/26 , G11C16/34
CPC分类号： G11C16/14 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C2211/5621 , H01L27/11582
摘要： Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.

12. 发明申请

US20160111164A1 Weak Erase After Programming To Improve Data Retention In Charge-Trapping Memory 有权
标题翻译：编程后弱化擦除电荷捕获存储器中的数据保留
公开(公告)号：US20160111164A1
公开(公告)日：2016-04-21
申请号：US14518340
申请日：2014-10-20
申请人： SANDISK TECHNOLOGIES INC.
发明人： Hong-Yan Chen , Yingda Dong , Ching-Huang Lu
IPC分类号： G11C16/14 , G11C16/04
CPC分类号： G11C16/14 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3404 , G11C16/3409 , G11C16/3413
摘要： Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.
摘要翻译：提供技术来改善电荷俘获存储器件中的长期数据保持。除了存储大多数电荷的主电荷捕获层之外，存储器件可以包括隧道层，其包括工程化隧道势垒，例如氧化物 - 氮化物 - 氧化物。在编程之后，隧道层中的氮化物也可能存储一些电荷。在编程之后，除了将空穴注入到形成中性电子 - 空穴偶极子的隧道层中以代替电子之外，还执行了从隧道层去除一些电子的数据保留操作。这些机制倾向于降低阈值电压。此外，数据保持操作将电荷和空穴重新分布在电荷俘获层内部，导致阈值电压的增加，这在数据保持操作优化时大致抵消了减少。

13. 发明申请

US20170330631A1 DUMMY WORD LINE CONTROL SCHEME FOR NON-VOLATILE MEMORY 有权
公开(公告)号：US20170330631A1
公开(公告)日：2017-11-16
申请号：US15151951
申请日：2016-05-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： Vinh Quang Diep , Liang Pang , Ching-Huang Lu , Yingda Dong
IPC分类号： G11C16/34 , G11C16/16 , G11C16/10 , G11C16/28 , G11C16/08
CPC分类号： G11C16/3431 , G11C7/04 , G11C7/14 , G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/28
摘要： A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or other issues, the memory system applies a gate voltage based on temperature to all or a subset of the dummy memory cells as part of a memory operation.

14. 发明授权

US09443861B1 Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures 有权
标题翻译：用于三维记忆结构背面接触结构的氟阻隔绝缘垫片
公开(公告)号：US09443861B1
公开(公告)日：2016-09-13
申请号：US14723919
申请日：2015-05-28
申请人： SANDISK TECHNOLOGIES, INC.
发明人： Jayavel Pachamuthu , Ching-Huang Lu , Johann Alsmeier
IPC分类号： H01L21/8238 , H01L27/115
CPC分类号： H01L27/11524 , H01L27/11529 , H01L27/11548 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11582
摘要： Electrical shorts caused by diffusion of residual fluorine in metallic layers can be retarded or eliminated by forming fluorine-blocking structures. A stack of alternating layers including electrically insulating layers and electrically conductive layers with a vertically extending trench is provided. In one embodiment, an insulating spacer can be formed by depositing a silicon nitride layer and partially or fully converting the silicon nitride layer into a silicon oxynitride layer, and by performing an anisotropic etch. Alternatively, an insulating spacer can be formed by forming a stack of a silicon nitride layer and a silicon oxide layer, and by performing an anisotropic etch. The silicon nitride layer or the silicon oxynitride layer can retard fluorine diffusion. Yet alternately, sidewalls of the electrically conductive layers can be nitrided to form metallic nitride portions that retard fluorine diffusion.
摘要翻译：通过形成氟阻断结构，可以延迟或消除由金属层中的残留氟扩散引起的电气短路。提供了包括电绝缘层和具有垂直延伸沟槽的导电层的交替层叠。在一个实施例中，可以通过沉积氮化硅层并且部分地或完全地将氮化硅层转化为氮氧化硅层并通过进行各向异性蚀刻来形成绝缘间隔物。或者，可以通过形成氮化硅层和氧化硅层的叠层并通过进行各向异性蚀刻来形成绝缘间隔物。氮化硅层或氮氧化硅层可以阻止氟扩散。或者，导电层的侧壁可以被氮化以形成延缓氟扩散的金属氮化物部分。

15. 发明申请

US20160172044A1 Method To Recover Cycling Damage And Improve Long Term Data Retention 有权
标题翻译：恢复循环伤害并改善长期数据保留的方法
公开(公告)号：US20160172044A1
公开(公告)日：2016-06-16
申请号：US14565729
申请日：2014-12-10
申请人： SanDisk Technologies Inc.
发明人： Ching-Huang Lu , Zhengyi Zhang , Wei Zhao , Yingda Dong , Jian Chen
IPC分类号： G11C16/16 , G11C16/04 , G11C16/32 , G11C16/34
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/0483 , G11C16/32 , G11C16/3431 , G11C16/3459 , G11C16/349 , G11C16/3495
摘要： Techniques for reversing damage caused by program-erase cycles in charge-trapping memory to improve long term data retention. A recovery process improves the data retention of a block of memory cells by programming the memory cells to a relatively high threshold voltage and enforcing a time period of several minutes or hours in which the memory cells are inactive and remain at the relatively high Vth levels. Damage such as traps in the memory cells is essentially healed or annealed out during this inactive period. All of the memory cells can be healed at the same time and by relatively equal amounts. At the conclusion of the recovery process, the block is returned to a pool of available blocks. In one approach, an amount of recovery is measured and the period of inactivity is continued for an amount of time which is based on the amount of recovery.
摘要翻译：用于在电荷捕获存储器中逆转由编程擦除周期引起的损坏以改善长期数据保持的技术。恢复过程通过将存储器单元编程到相对较高的阈值电压并且执行存储器单元不活动并保持在相对高的Vth电平的几分钟或数小时的时间段来改善存储器单元块的数据保持。在这个不活跃的时期，诸如记忆单元中的陷阱的损伤基本上被愈合或退火。所有的记忆细胞可以同时和相对相等的量治愈。在恢复过程结束时，块将返回到可用块池。在一种方法中，测量恢复量，并且基于回收量，持续不活动的时间持续一段时间。

16. 发明授权

US09312010B1 Programming of drain side word line to reduce program disturb and charge loss 有权
标题翻译：编程漏极字线，减少程序干扰和电荷损失
公开(公告)号：US09312010B1
公开(公告)日：2016-04-12
申请号：US14508164
申请日：2014-10-07
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Yingda Dong , Ching-Huang Lu , Wei Zhao
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.
摘要翻译：提供了在编程集合的任何其他字线的存储器单元之前对一组字线集合的漏极边缘字线的存储器单元进行编程的技术。施加到其它字线的通过电压作为应力脉冲，其重新分配其它字线的存储单元的电荷捕获材料中的空穴，以减少阈值电压的短期电荷损耗和降档。此外，用于漏极侧边缘字线的一个或多个初始编程电压相对较低并且还用作应力脉冲。漏极侧边缘字线的存储单元被编程到比其它字线的存储单元窄的Vth窗口。这由于减少的信道增强而补偿了漏极侧边缘字线的擦除状态存储单元的编程干扰的较高水平。

17. 发明申请

US20160064084A1 Programming Memory With Reduced Short-Term Charge Loss 有权
标题翻译：编程内存减少短期电荷损失
公开(公告)号：US20160064084A1
公开(公告)日：2016-03-03
申请号：US14925473
申请日：2015-10-28
申请人： SanDisk Technologies Inc.
发明人： Ching-Huang Lu , Yingda Dong , Liang Pang , Tien-Chien Kuo
IPC分类号： G11C16/10 , G11C16/04 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0466 , G11C16/3404 , G11C16/3459
摘要： Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.
摘要翻译：提供了在编程电荷捕获存储器单元的同时减少短期电荷损失的影响的技术。短时间的电荷损失可导致门限电压分布的降档和加宽。对于每个目标数据状态，编程操作包括粗略编程通过，其中存储器单元被编程为接近最终阈值电压分布。随后，将负电压施加到存储器单元的控制栅极。随后，执行最终编程遍，其中将存储器单元编程为最终阈值电压分布。由于负电压加速电荷损失，所以在最终编程通过后电荷损失减小。粗略编程通道可以使用增量步进脉冲编程来获得最低目标数据状态，以获得有关编程速度的信息。可以根据编程速度设置最终编程遍历中的初始编程电压。

18. 发明授权

US09230663B1 Programming memory with reduced short-term charge loss 有权
标题翻译：编程内存减少短期电荷损失
公开(公告)号：US09230663B1
公开(公告)日：2016-01-05
申请号：US14472872
申请日：2014-08-29
申请人： SanDisk Technologies Inc.
发明人： Ching-Huang Lu , Yingda Dong , Liang Pang , Tien-Chien Kuo
IPC分类号： G11C16/00 , G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0466 , G11C16/3404 , G11C16/3459
摘要： Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.
摘要翻译：提供了在编程电荷捕获存储器单元的同时减少短期电荷损失的影响的技术。短时间的电荷损失可导致门限电压分布的降档和加宽。对于每个目标数据状态，编程操作包括粗略编程通过，其中存储器单元被编程为接近最终阈值电压分布。随后，将负电压施加到存储器单元的控制栅极。随后，执行最终编程遍，其中将存储器单元编程为最终阈值电压分布。由于负电压加速电荷损失，所以在最终编程通过后电荷损失减小。粗略编程通道可以使用增量步进脉冲编程来获得最低目标数据状态，以获得有关编程速度的信息。可以根据编程速度设置最终编程遍历中的初始编程电压。

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