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11. 发明授权

US06901549B2 Method for altering a word stored in a write-once memory device 失效
标题翻译：用于改变存储在一次写入存储器件中的字的方法
公开(公告)号：US06901549B2
公开(公告)日：2005-05-31
申请号：US10023200
申请日：2001-12-14
申请人： Roger W. March , Christopher S. Moore , Mark G. Johnson
发明人： Roger W. March , Christopher S. Moore , Mark G. Johnson
IPC分类号： G11C7/10 , G11C7/24 , G11C17/14 , H03M13/00
CPC分类号： G11C17/146 , G11C7/1006 , G11C7/24 , G11C17/14
摘要： The preferred embodiments described herein provide a method for altering a word stored in a write-once memory device. In one preferred embodiment, a write-once memory device is provided storing a word comprising a plurality of data bits and a plurality of syndrome bits. The word is altered by identifying X bit(s) in the word that are in an un-programmed state and switching the X bit(s) from the un-programmed state to a programmed state, where X is sufficient to introduce an uncorrectable error in the word. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：本文所述的优选实施例提供了一种用于改变存储在一次写入存储器件中的字的方法。在一个优选实施例中，提供了一次写入存储器件，其存储包括多个数据位和多个校正子位的字。通过识别字处于非编程状态的X位，并将X位从未编程状态切换到编程状态来改变该字，其中X足以引入不可校正的错误在这个词中。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

12. 发明授权

US06515904B2 Method and system for increasing programming bandwidth in a non-volatile memory device 有权
公开(公告)号：US06515904B2
公开(公告)日：2003-02-04
申请号：US09895960
申请日：2001-06-29
申请人： Christopher S. Moore , Bendik Kleveland , Roger W. March , James M. Cleeves , Roy E. Scheuerlein
发明人： Christopher S. Moore , Bendik Kleveland , Roger W. March , James M. Cleeves , Roy E. Scheuerlein
IPC分类号： G11C1600
CPC分类号： G11C8/08 , G11C7/062 , G11C7/067 , G11C7/18 , G11C16/10 , G11C2207/063
摘要： The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

13. 发明授权

US07003619B1 Memory device and method for storing and reading a file system structure in a write-once memory array 有权
标题翻译：用于在一次写入存储器阵列中存储和读取文件系统结构的存储器件和方法
公开(公告)号：US07003619B1
公开(公告)日：2006-02-21
申请号：US09877719
申请日：2001-06-08
申请人： Christopher S. Moore , James E. Schneider , J. James Tringali , Roger W. March
发明人： Christopher S. Moore , James E. Schneider , J. James Tringali , Roger W. March
IPC分类号： G11C7/00 , G11C11/34
CPC分类号： G11C17/146 , G11C7/1006 , G11C17/16 , Y10S707/99953
摘要： The preferred embodiments described herein provide a memory device and method for storing and reading a file system structure in a write-once memory array. In one preferred embodiment, a plurality of bits representing a file system structure is inverted and stored in a write-once memory array. When the inverted plurality of bits is read from the memory array, the bits are inverted to provide the file system structure bits in their original, non-inverted configuration. With this preferred embodiment, a file system structure can be updated to reflect data stored in the memory array after the file system structure was written. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
摘要翻译：本文描述的优选实施例提供了一种用于在一次写入存储器阵列中存储和读取文件系统结构的存储器件和方法。在一个优选实施例中，表示文件系统结构的多个位被反转并存储在一次写入存储器阵列中。当从存储器阵列中读出反相多位时，这些位被反转，以提供其原始的非倒置配置的文件系统结构位。利用该优选实施例，可以更新文件系统结构以在写入文件系统结构之后反映存储在存储器阵列中的数据。提供了其它优选实施方案，并且本文所述的各优选实施方案可以单独使用或彼此组合使用。

14. 发明授权

US4649470A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US4649470A
公开(公告)日：1987-03-10
申请号：US435385
申请日：1982-10-20
申请人： David H. Bernstein , Edward M. Buckley , Roger W. March , Ronald I. Gusowski, deceased
发明人： David H. Bernstein , Edward M. Buckley , Roger W. March , Ronald I. Gusowski, deceased
IPC分类号： G06F9/26 , G06F13/36 , G06F13/42 , H03K23/66 , G06F13/38
CPC分类号： H03K23/667 , G06F13/36 , G06F13/4217 , G06F9/26
摘要： A data processing system using microcode architecture in which a two-level microcode system comprises one or more first, or "horizontal", microinstructions and a plurality of second, or "vertical", microinstruction portions in a vertical microcontrol store. In a preferred embodiment the vertical microinstruction portions include one or more "modifier" fields, a selection field for selecting a horizontal microinstruction and a sequencing field for selecting the next vertical microinstruction portion of a sequence thereof, one or more fields of the horizontal microinstructions being capable of modification by the vertical modifier fields in order to form output microinstructions for performing data processing operations. Unique bus protocol signals are generated to prevent simultaneous access to the system bus by two competing system components and to permit substantially immediate control of the systems bus by a component without requiring a CPU decision thereon. Further, a unique system I/O interface unit permits access to certain I/O components via other I/O buses, such unit utilizing a unique polling technique to identify on an updated basis, all components present on one of such other buses. The system I/O interface unit also includes a unique frequency synthesizer unit for providing at least one clock signal having a substantially constant frequency which can be generated in response to any one of a plurality of input clock signals each having a different frequency.
摘要翻译：一种使用微代码架构的数据处理系统，其中两级微代码系统包括垂直微控制器存储器中的一个或多个第一或“水平”微指令以及多个第二或“垂直”微指令部分。在优选实施例中，垂直微指令部分包括一个或多个“修改器”字段，用于选择水平微指令的选择字段和用于选择其序列的下一垂直微指令部分的测序字段，水平微指令的一个或多个字段为能够通过垂直修改器字段进行修改，以便形成用于执行数据处理操作的输出微指令。产生独特的总线协议信号以防止由两个竞争的系统组件同时访问系统总线，并允许由组件基本上立即控制系统总线，而不需要CPU决定。此外，独特的系统I / O接口单元允许通过其他I / O总线访问某些I / O组件，这种单元利用独特的轮询技术，以更新的方式识别存在于其中一个其它总线上的所有组件。系统I / O接口单元还包括唯一的频率合成器单元，用于提供至少一个具有基本上恒定频率的时钟信号，该时钟信号可以响应于具有不同频率的多个输入时钟信号中的任何一个而产生。

15. 发明授权

US4464772A Frequency synthesizer for providing a pseudo-constant frequency signal 失效
标题翻译：用于提供伪恒定频率信号的频率合成器
公开(公告)号：US4464772A
公开(公告)日：1984-08-07
申请号：US120291
申请日：1980-02-11
申请人： Edward M. Buckley , Michael B. Druke , Roger W. March
发明人： Edward M. Buckley , Michael B. Druke , Roger W. March
IPC分类号： G06F9/26 , G06F13/36 , G06F13/42 , H03K23/66 , H03K21/36
CPC分类号： H03K23/667 , G06F13/36 , G06F13/42 , G06F9/26
摘要： A unique frequency synthesizer unit for use in a data processing system I/O interface unit for providing at least one clock signal having a substantially constant frequency which can be generated in response to any one of a plurality of input clock signals each having a different frequency. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics. The system I/O interface unit may be used, for example, to control communication between a system bus and a plurality of I/O buses having different timing and operating characteristics.
摘要翻译：一种独特的频率合成器单元，用于在数据处理系统I / O接口单元中使用，用于提供至少一个具有基本上恒定频率的时钟信号，该时钟信号可以响应于具有不同频率的多个输入时钟信号中的任何一个而产生。例如，系统I / O接口单元可以用于控制系统总线与具有不同时序和操作特性的多个I / O总线之间的通信。例如，系统I / O接口单元可以用于控制系统总线与具有不同时序和操作特性的多个I / O总线之间的通信。

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