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11. 发明授权

US08555038B2 Processor and method providing instruction support for instructions that utilize multiple register windows 有权
标题翻译：处理器和方法为使用多个寄存器窗口的指令提供指令支持
公开(公告)号：US08555038B2
公开(公告)日：2013-10-08
申请号：US12790074
申请日：2010-05-28
申请人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
发明人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
IPC分类号： G06F9/00
CPC分类号： G06F9/30127 , G06F7/5324 , G06F9/30032 , G06F9/30043 , G06F9/30145 , G06F9/3824 , G06F9/384 , G06F9/3844 , G06F9/3851 , G06F9/3867 , G06F21/556
摘要： A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction execution unit that, during operation, receives instructions for execution from the instruction fetch unit and executes a large-operand instruction defined within the ISA, where execution of the large-operand instruction is dependent upon a plurality of registers arranged within a plurality of register windows. The processor may further include control circuitry (which may be included within the fetch unit, the execution unit, or elsewhere within the processor) that determines whether one or more of the register windows depended upon by the large-operand instruction are not present. In response to determining that one or more of these register windows are not present, the control circuitry causes them to be restored.
摘要翻译：包括对使用多个寄存器窗口的大操作数指令的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的指令。处理器还可以包括指令执行单元，其在操作期间从指令获取单元接收执行指令，并执行在ISA内定义的大操作数指令，其中大操作数指令的执行取决于多个寄存器布置在多个寄存器窗口内。处理器还可以包括控制电路（其可以包括在提取单元，执行单元或处理器内的其他地方），其确定不存在大操作数指令所依赖的寄存器窗口中的一个或多个。响应于确定这些寄存器窗口中的一个或多个不存在，控制电路使它们被恢复。

12. 发明授权

US08301865B2 System and method to manage address translation requests 有权
标题翻译：管理地址转换请求的系统和方法
公开(公告)号：US08301865B2
公开(公告)日：2012-10-30
申请号：US12493941
申请日：2009-06-29
申请人： Gregory F. Grohoski , Paul J. Jordan , Mark A. Luttrell , Zeid Hartuon Samoail , Robert T. Golla
发明人： Gregory F. Grohoski , Paul J. Jordan , Mark A. Luttrell , Zeid Hartuon Samoail , Robert T. Golla
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/1027 , G06F2212/684
摘要： A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses and a data-related portion storing entries for potential or actual data TLB (DTLB) misses. A DTLB PRQ entry may be allocated to each load/store instruction selected from the pick queue. The system may select an ITLB- or DTLB-related entry for servicing dependent on prior PRQ entry selection(s). A corresponding entry may be held in a translation table entry return queue (TTERQ) in the output pipeline until a matching address translation is received from system memory. PRQ and/or TTERQ entries may be deallocated when a corresponding TLB miss is serviced. PRQ and/or TTERQ entries associated with a thread may be deallocated in response to a thread flush.
摘要翻译：用于服务翻译后备缓冲器（TLB）的系统和方法可以管理存储器管理单元内的单独的输入和输出管线。输入流水线中的未决请求队列（PRQ）可以包括存储用于指令TLB（ITLB）未命中的条目的指令相关部分和存储潜在或实际数据TLB（DTLB）丢失的条目的数据相关部分。可以将DTLB PRQ条目分配给从拾取队列中选择的每个加载/存储指令。系统可以根据先前的PRQ条目选择来选择与ITLB或DTLB相关的条目进行服务。相应的条目可以保存在输出流水线中的转换表条目返回队列（TTERQ）中，直到从系统存储器接收到匹配的地址转换。当服务对应的TLB未命中时，PRQ和/或TTERQ条目可以被释放。与线程相关联的PRQ和/或TTERQ条目可以响应于线程刷新而被释放。

13. 发明授权

US07426630B1 Arbitration of window swap operations 有权
标题翻译：窗口交换操作的仲裁
公开(公告)号：US07426630B1
公开(公告)日：2008-09-16
申请号：US10881151
申请日：2004-06-30
申请人： Jike Chong , Robert T. Golla , Paul J. Jordan
发明人： Jike Chong , Robert T. Golla , Paul J. Jordan
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/30116 , G06F9/3012 , G06F9/30127
摘要： In one embodiment, a processor comprises a register file, register management logic coupled to the register file, and at least two sources of window swap operations coupled to the register management logic. The register management logic is configured to control an interface to the register file to switch register windows in the register file in response to one or more window swap operations. The sources of window swap operations and the register management logic are configured to cooperate according to an arbitration scheme to arbitrate between conflicting window swap operations to be performed using the interface. In one particular implementation, for example, block signals may be used from higher priority sources to lower priority sources to block issuance of window swap operations by the lower priority sources.
摘要翻译：在一个实施例中，处理器包括寄存器文件，耦合到寄存器文件的寄存器管理逻辑以及耦合到寄存器管理逻辑的至少两个窗口交换源。寄存器管理逻辑被配置为响应于一个或多个窗口交换操作来控制寄存器文件的接口来切换寄存器文件中的寄存器窗口。窗口交换操作的来源和寄存器管理逻辑被配置为根据仲裁方案进行协作以在使用该接口执行的冲突的窗口交换操作之间进行仲裁。在一个特定实现中，例如，可以使用块信号从较高优先级源降低优先级源，以阻止较低优先级源发出窗口交换操作。

14. 发明授权

US07350053B1 Software accessible fast VA to PA translation 有权
标题翻译：软件可访问快速VA到PA翻译
公开(公告)号：US07350053B1
公开(公告)日：2008-03-25
申请号：US11034345
申请日：2005-01-11
申请人： Rabin A. Sugumar , Robert T. Golla , Paul J. Jordan
发明人： Rabin A. Sugumar , Robert T. Golla , Paul J. Jordan
IPC分类号： G06F9/26 , G06F9/34 , G06F12/00
CPC分类号： G06F12/1081 , G06F12/1027
摘要： A method to communicate data is disclosed which includes communicating a virtual address to a translation lookaside buffer (TLB) and translating the virtual address to a physical address of a computer memory. The method also includes loading the physical address translated by the TLB into a register within a processor and transmitting the data from the physical address to a destination computing device.
摘要翻译：公开了一种用于传送数据的方法，其包括将虚拟地址传送到翻译后备缓冲器（TLB）并将虚拟地址转换为计算机存储器的物理地址。该方法还包括将由TLB转换的物理地址加载到处理器内的寄存器中，并将数据从物理地址传输到目标计算设备。

15. 发明授权

US08438208B2 Processor and method for implementing instruction support for multiplication of large operands 有权
标题翻译：用于实现大操作数乘法的指令支持的处理器和方法
公开(公告)号：US08438208B2
公开(公告)日：2013-05-07
申请号：US12488372
申请日：2009-06-19
申请人： Christopher H. Olson , Jeffrey S. Brooks , Robert T. Golla , Paul J. Jordan
发明人： Christopher H. Olson , Jeffrey S. Brooks , Robert T. Golla , Paul J. Jordan
IPC分类号： G06F7/52 , G06F7/38
CPC分类号： G06F7/4876 , G06F2207/382
摘要： A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M. In response to receiving a single instance of a large-operand multiplication instruction defined within the ISA, wherein at least one of the operands of the large-operand multiplication instruction includes more than the maximum number of bits M, the instruction execution unit is configured to multiply operands of the large-operand multiplication instruction within the hardware multiplier datapath circuit to determine a result of the large-operand multiplication instruction without execution of programmer-selected instructions within the ISA other than the large-operand multiplication instruction.
摘要翻译：包括用于实现大操作数乘法的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的执行。处理器可以包括指令执行单元，其包括硬件乘法器数据路径电路，其中硬件乘法器数据路径电路被配置为对具有最大位数M的操作数进行乘法。响应于接收到在其中定义的大操作数乘法指令的单个实例所述ISA，其中所述大操作数乘法指令的操作数中的至少一个包括多于所述最大位数M，所述指令执行单元被配置为将所述大操作数乘法指令在所述硬件乘法器数据通路电路内的操作数乘以确定大操作数乘法指令的结果，而不在大操作数乘法指令之外执行ISA内的编程器选择指令。

16. 发明申请

US20100332787A1 System and Method to Manage Address Translation Requests 有权
标题翻译：管理地址转换请求的系统和方法
公开(公告)号：US20100332787A1
公开(公告)日：2010-12-30
申请号：US12493941
申请日：2009-06-29
申请人： Gregory F. Grohoski , Paul J. Jordan , Mark A. Luttrell , Zeid Hartuon Samoail , Robert T. Golla
发明人： Gregory F. Grohoski , Paul J. Jordan , Mark A. Luttrell , Zeid Hartuon Samoail , Robert T. Golla
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1027 , G06F2212/684
摘要： A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses and a data-related portion storing entries for potential or actual data TLB (DTLB) misses. A DTLB PRQ entry may be allocated to each load/store instruction selected from the pick queue. The system may select an ITLB- or DTLB-related entry for servicing dependent on prior PRQ entry selection(s). A corresponding entry may be held in a translation table entry return queue (TTERQ) in the output pipeline until a matching address translation is received from system memory. PRQ and/or TTERQ entries may be deallocated when a corresponding TLB miss is serviced. PRQ and/or TTERQ entries associated with a thread may be deallocated in response to a thread flush.
摘要翻译：用于服务翻译后备缓冲器（TLB）的系统和方法可以管理存储器管理单元内的单独的输入和输出管线。输入流水线中的未决请求队列（PRQ）可以包括存储用于指令TLB（ITLB）未命中的条目的指令相关部分和存储潜在或实际数据TLB（DTLB）丢失的条目的数据相关部分。可以将DTLB PRQ条目分配给从拾取队列中选择的每个加载/存储指令。系统可以根据先前的PRQ条目选择来选择与ITLB或DTLB相关的条目进行服务。相应的条目可以保存在输出流水线中的转换表条目返回队列（TTERQ）中，直到从系统存储器接收到匹配的地址转换。当服务对应的TLB未命中时，PRQ和/或TTERQ条目可以被释放。与线程相关联的PRQ和/或TTERQ条目可以响应于线程刷新而被释放。

17. 发明申请

US20100325188A1 PROCESSOR AND METHOD FOR IMPLEMENTING INSTRUCTION SUPPORT FOR MULTIPLICATION OF LARGE OPERANDS 有权
标题翻译：用于实施大规模操作的指导性支持的处理器和方法
公开(公告)号：US20100325188A1
公开(公告)日：2010-12-23
申请号：US12488372
申请日：2009-06-19
申请人： Christopher H. Olson , Jeffrey S. Brooks , Robert T. Golla , Paul J. Jordan
发明人： Christopher H. Olson , Jeffrey S. Brooks , Robert T. Golla , Paul J. Jordan
IPC分类号： G06F7/52
CPC分类号： G06F7/4876 , G06F2207/382
摘要： A processor including instruction support for implementing large-operand multiplication may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include an instruction execution unit comprising a hardware multiplier datapath circuit, where the hardware multiplier datapath circuit is configured to multiply operands having a maximum number of bits M. In response to receiving a single instance of a large-operand multiplication instruction defined within the ISA, wherein at least one of the operands of the large-operand multiplication instruction includes more than the maximum number of bits M, the instruction execution unit is configured to multiply operands of the large-operand multiplication instruction within the hardware multiplier datapath circuit to determine a result of the large-operand multiplication instruction without execution of programmer-selected instructions within the ISA other than the large-operand multiplication instruction.
摘要翻译：包括用于实现大操作数乘法的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的执行。处理器可以包括指令执行单元，其包括硬件乘法器数据路径电路，其中硬件乘法器数据路径电路被配置为对具有最大位数M的操作数进行乘法。响应于接收到在其中定义的大操作数乘法指令的单个实例所述ISA，其中所述大操作数乘法指令的操作数中的至少一个包括多于所述最大位数M，所述指令执行单元被配置为将所述大操作数乘法指令在所述硬件乘法器数据通路电路内的操作数乘以确定大操作数乘法指令的结果，而不在大操作数乘法指令之外执行ISA内的编程器选择指令。

18. 发明授权

US08412911B2 System and method to invalidate obsolete address translations 有权
标题翻译：使过时地址转换无效的系统和方法
公开(公告)号：US08412911B2
公开(公告)日：2013-04-02
申请号：US12493923
申请日：2009-06-29
申请人： Gregory F. Grohoski , Paul J. Jordan , Mark A. Luttrell , Zeid Hartuon Samoail
发明人： Gregory F. Grohoski , Paul J. Jordan , Mark A. Luttrell , Zeid Hartuon Samoail
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3851 , G06F9/3885 , G06F12/1027 , G06F2212/683
摘要： A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in response to changes in the virtual memory space, and thus may need to be demapped. A non-cacheable unit (NCU) residing on a processor may be configured to receive and manage a global TLB demap request from a thread executing on a core residing on the processor. The NCU may send the request to local cores and/or to NCUs of external processors in a multiprocessor system using a hardware instruction to broadcast to all cores and/or processors or to multicast to designated cores and/or processors. The NCU may track completion of the demap operation across the cores and/or processors using one or more counters, and may send an acknowledgement to the initiator of the demap request when the global demap request has been satisfied.
摘要翻译：将过时的虚拟/实际地址无效化到物理地址转换的系统和方法可以使用翻译后备缓冲器来缓存翻译。 TLB条目可以响应于虚拟存储器空间的变化而被无效，因此可能需要进行解映射。驻留在处理器上的不可缓存单元（NCU）可以被配置为从驻留在处理器上的核上执行的线程接收和管理全局TLB解映射请求。 NCU可以使用硬件指令向多处理器系统中的本地核心和/或外部处理器的NCU发送请求，以广播到所有核心和/或处理器或者组播到指定的核心和/或处理器。 NCU可以跟踪使用一个或多个计数器的核心和/或处理器之间的去映射操作的完成，并且当满足全局解映射请求时，可以向解映射请求的发起者发送确认。

19. 发明申请

US20120246437A1 METHOD AND APPARATUS FOR USING UNUSED BITS IN A MEMORY POINTER 有权
标题翻译：在存储器中使用未使用位的方法和装置
公开(公告)号：US20120246437A1
公开(公告)日：2012-09-27
申请号：US13069337
申请日：2011-03-22
申请人： Zoran Radovic , Graham Ricketson Murphy , Paul J. Jordan , John G. Johnson
发明人： Zoran Radovic , Graham Ricketson Murphy , Paul J. Jordan , John G. Johnson
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/10 , G06F8/315 , G06F12/02 , G06F12/0253
摘要： The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.
摘要翻译：所公开的实施例提供了使用存储器指针中的未使用位的系统。在操作期间，系统确定地址空间中的一组地址位，在编程操作期间不需要寻址目的。随后，系统将与存储器指针相关联的数据存储在该组地址位中。当使用存储器指针访问与存储器指针相关联的存储器地址时，系统将对该组地址位进行掩蔽。将附加数据存储在未使用的指针位中可以减少程序的存储器访问次数，并提高程序性能和/或可靠性。

20. 发明授权

US08190864B1 APIC implementation for a highly-threaded x86 processor 有权
标题翻译：高性能x86处理器的APIC实现
公开(公告)号：US08190864B1
公开(公告)日：2012-05-29
申请号：US11924491
申请日：2007-10-25
申请人： Paul J. Jordan , Gregory F. Grohoski
发明人： Paul J. Jordan , Gregory F. Grohoski
IPC分类号： G06F9/00
CPC分类号： G06F9/4818
摘要： Advanced programmable interrupt control for a multithreaded multicore processor that supports software compatible with x86 processors. Embodiments provide interrupt control for increased threads with minimal additional hardware by including in each processor core, a core advanced interrupt controller (core APIC) configured to determine a lowest priority thread of its corresponding processor core. Each core APIC reports its lowest priority thread level as a core priority to an input/output APIC. The I/O APIC routes interrupt requests to the core APIC with the lowest core priority. The selected core APIC then routes the interrupt request to the corresponding lowest priority thread. Each core APIC detects changes in priority levels of its corresponding processor core threads, and notifies the I/O APIC of any change to the corresponding core priority. Each core APIC may notify the I/O APIC as the core priority changes, or when the I/O APIC requests status from each core APIC.
摘要翻译：用于支持与x86处理器兼容的软件的多线程多核处理器的高级可编程中断控制。实施例通过在每个处理器核心中包括被配置为确定其对应的处理器核心的最低优先级线程的核心高级中断控制器（核心APIC）来提供具有最小附加硬件的增加的线程的中断控制。每个核心APIC报告其最低优先级线程级别作为输入/输出APIC的核心优先级。 I / O APIC将核心优先级最低的核心APIC路由中断请求。所选的核心APIC然后将中断请求路由到相应的最低优先级线程。每个核心APIC检测其对应的处理器核心线程的优先级别的变化，并将I / O APIC通知相应的核心优先级的任何更改。当核心优先级改变时，或者当I / O APIC从每个核心APIC请求状态时，每个核心APIC可以通知I / O APIC。

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