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1. 发明授权

US07426630B1 Arbitration of window swap operations 有权
标题翻译：窗口交换操作的仲裁
公开(公告)号：US07426630B1
公开(公告)日：2008-09-16
申请号：US10881151
申请日：2004-06-30
申请人： Jike Chong , Robert T. Golla , Paul J. Jordan
发明人： Jike Chong , Robert T. Golla , Paul J. Jordan
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/3851 , G06F9/30116 , G06F9/3012 , G06F9/30127
摘要： In one embodiment, a processor comprises a register file, register management logic coupled to the register file, and at least two sources of window swap operations coupled to the register management logic. The register management logic is configured to control an interface to the register file to switch register windows in the register file in response to one or more window swap operations. The sources of window swap operations and the register management logic are configured to cooperate according to an arbitration scheme to arbitrate between conflicting window swap operations to be performed using the interface. In one particular implementation, for example, block signals may be used from higher priority sources to lower priority sources to block issuance of window swap operations by the lower priority sources.
摘要翻译：在一个实施例中，处理器包括寄存器文件，耦合到寄存器文件的寄存器管理逻辑以及耦合到寄存器管理逻辑的至少两个窗口交换源。寄存器管理逻辑被配置为响应于一个或多个窗口交换操作来控制寄存器文件的接口来切换寄存器文件中的寄存器窗口。窗口交换操作的来源和寄存器管理逻辑被配置为根据仲裁方案进行协作以在使用该接口执行的冲突的窗口交换操作之间进行仲裁。在一个特定实现中，例如，可以使用块信号从较高优先级源降低优先级源，以阻止较低优先级源发出窗口交换操作。

2. 发明授权

US08566259B2 Method and system for parallel statistical inference on highly parallel platforms 有权
标题翻译：高度并行平台并行统计推理的方法与系统
公开(公告)号：US08566259B2
公开(公告)日：2013-10-22
申请号：US12876898
申请日：2010-09-07
申请人： Jike Chong , Youngmin Yi , Ekaterina I. Gonina
发明人： Jike Chong , Youngmin Yi , Ekaterina I. Gonina
IPC分类号： G06N5/00
CPC分类号： G06N99/005
摘要： Methods for faster statistical inference in computation based recognition problems on highly parallel processors with multiple cores on-a-chip are disclosed, which include: selectively flattening levels of the recognition network to improve inference speed (improving the recognition model); selectively duplicating parts of the recognition network to minimize a critical section in atomic accesses to as few as one atomic instruction (improving the recognition procedure); and combining weight and source port into one 32-bit word to minimize the number of atomic operations. These methods have been implemented on an NVIDIA GTX 280 processor in a Large Vocabulary Continuous Speech Recognition (LVCSR) embodiment, and achieve more than a 10× speed up compared to a highly optimized sequential implementation on an Intel Core i7 processor.
摘要翻译：公开了一种在片上具有多个芯片的高度并行处理器上基于计算的识别问题的统计推理的方法，其中包括：选择性地平坦化识别网络的级别，以提高推理速度（提高识别模型）; 选择性地复制识别网络的部分以使原子访问中的关键部分最小化到少至一个原子指令（改善识别过程）; 并将权重和源端口组合成一个32位字以最小化原子操作的数量。这些方法已经在大型词汇连续语音识别（LVCSR）实施例中的NVIDIA GTX 280处理器上实现，并且与Intel Core i7处理器上的高度优化的顺序实现相比，实现了超过10倍的速度。

3. 发明申请

US20110066578A1 METHOD AND SYSTEM FOR PARALLEL STATISTICAL INFERENCE ON HIGHLY PARALLEL PLATFORMS 有权
标题翻译：高平行平台平行统计学方法与系统
公开(公告)号：US20110066578A1
公开(公告)日：2011-03-17
申请号：US12876898
申请日：2010-09-07
申请人： Jike Chong , Youngmin Yi , Ekaterina I. Gonina
发明人： Jike Chong , Youngmin Yi , Ekaterina I. Gonina
IPC分类号： G06F15/18 , G06N5/04
CPC分类号： G06N99/005
摘要： Methods for faster statistical inference in computation based recognition problems on highly parallel processors with multiple cores on-a-chip are disclosed, which include: selectively flattening levels of the recognition network to improve inference speed (improving the recognition model); selectively duplicating parts of the recognition network to minimize a critical section in atomic accesses to as few as one atomic instruction (improving the recognition procedure); and combining weight and source port into one 32-bit word to minimize the number of atomic operations. These methods have been implemented on an NVIDIA GTX 280 processor in a Large Vocabulary Continuous Speech Recognition (LVCSR) embodiment, and achieve more than a 10× speed up compared to a highly optimized sequential implementation on an Intel Core i7 processor.
摘要翻译：公开了一种在片上具有多个芯片的高度并行处理器上基于计算的识别问题的统计推理的方法，其中包括：选择性地平坦化识别网络的级别，以提高推理速度（提高识别模型）; 选择性地复制识别网络的部分以使原子访问中的关键部分最小化到少至一个原子指令（改善识别过程）; 并将权重和源端口组合成一个32位字以最小化原子操作的数量。这些方法已经在大型词汇连续语音识别（LVCSR）实施例中的NVIDIA GTX 280处理器上实现，并且与Intel Core i7处理器上的高度优化的顺序实现相比，实现了超过10倍的速度。

4. 发明申请

US20100082939A1 TECHNIQUES FOR EFFICIENT IMPLEMENTATION OF BROWNIAN BRIDGE ALGORITHM ON SIMD PLATFORMS 审中-公开
标题翻译：在SIMD平台上有效实施BROWNIAN BRIDGE算法的技术
公开(公告)号：US20100082939A1
公开(公告)日：2010-04-01
申请号：US12242411
申请日：2008-09-30
申请人： Jike Chong , Mikhail Smelyanskiy , Ram Ramanujam , Victor Lee
发明人： Jike Chong , Mikhail Smelyanskiy , Ram Ramanujam , Victor Lee
IPC分类号： G06F15/00
CPC分类号： G06F17/10
摘要： Methods and apparatus for implementing Brownian Bridge algorithm on Single Instruction Multiple Data (SIMD) computing platforms are described. In one embodiment, a memory stores a plurality of data corresponding to an SIMD (Single Instruction, Multiple Data) instruction. A processor may include a plurality of SIMD lanes. Each of the plurality of the SIMD lanes may process one of the plurality of data stored in the memory in accordance with the SIMD instruction. Other embodiments are also described.
摘要翻译：描述了单指令多数据（SIMD）计算平台实现布朗桥算法的方法和装置。在一个实施例中，存储器存储对应于SIMD（单指令，多数据）指令的多个数据。处理器可以包括多个SIMD通道。多个SIMD通道中的每一个可以根据SIMD指令处理存储在存储器中的多个数据之一。还描述了其它实施例。

5. 发明授权

US07353364B1 Apparatus and method for sharing a functional unit execution resource among a plurality of functional units 有权
标题翻译：在多个功能单元中共享功能单元执行资源的装置和方法
公开(公告)号：US07353364B1
公开(公告)日：2008-04-01
申请号：US10881261
申请日：2004-06-30
申请人： Jike Chong , Christopher Olson , Gregory F. Grohoski
发明人： Jike Chong , Christopher Olson , Gregory F. Grohoski
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/30014 , G06F9/30145 , G06F9/3802 , G06F9/3824 , G06F9/3826 , G06F9/3877 , G06F9/3885 , G06F21/71 , G06F2221/2141
摘要： An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to execute instructions issued from the instruction fetch logic and to execute operations issued from a second functional unit, where the operations are issued asynchronously with respect to the instructions. The second functional unit may be configured to provide one or more operands corresponding to a given operation to the first functional unit. The first functional unit may include temporary result storage configured to store a result of the given operation while the first functional unit executes a given instruction issued from the instruction fetch logic, and the first functional unit may be further configured to use the stored result as an operand of an operation issued subsequently to the given operation.
摘要翻译：一种用于共享功能单元的装置和方法。在一个实施例中，处理器可以包括被配置为发出指令的指令提取逻辑，以及被配置为执行从指令提取逻辑发出的指令并且执行从第二功能单元发出的操作的第一功能单元，其中操作相对于指示。第二功能单元可以被配置为向第一功能单元提供对应于给定操作的一个或多个操作数。第一功能单元可以包括被配置为在第一功能单元执行从指令提取逻辑发出的给定指令时存储给定操作的结果的临时结果存储器，并且第一功能单元可以被进一步配置为将存储的结果用作在给定操作之后发出的操作的操作数。

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