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11. 发明申请

US20090087999A1 TECHNIQUE FOR COMPENSATING FOR A DIFFERENCE IN DEPOSITION BEHAVIOR IN AN INTERLAYER DIELECTRIC MATERIAL 有权
标题翻译：用于补偿中间层介质材料中沉积行为差异的技术
公开(公告)号：US20090087999A1
公开(公告)日：2009-04-02
申请号：US12168443
申请日：2008-07-07
申请人： Ralf Richter , Robert Seidel , Carsten Peters
发明人： Ralf Richter , Robert Seidel , Carsten Peters
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/76819 , H01L21/76829 , H01L21/76832 , H01L29/7843
摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.
摘要翻译：通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料作为有效的蚀刻停止层。

12. 发明申请

US20120220119A1 SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS 有权
标题翻译：用于在常见蚀刻过程中绘制垂直接触和金属线的半导体器件和方法
公开(公告)号：US20120220119A1
公开(公告)日：2012-08-30
申请号：US13468083
申请日：2012-05-10
申请人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
发明人： Ralf Richter , Robert Seidel , Juergen Boemmels , Thomas Foltyn
IPC分类号： H01L21/768 , H01L21/308
CPC分类号： H01L21/7681 , H01L21/76811 , H01L21/76816
摘要： Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.
摘要翻译：中间层连接（即垂直连接）可以基于硬掩模材料形成，硬掩模材料可以位于层间电介质材料的内部或之上，其中一个横向尺寸由沟槽掩模限定，从而获得所需的中间层连接在共同的图案化过程中。此外，金属线的至少某些部分的厚度可以以高度的柔性来调节，从而提供了显着降低金属线中金属线的整体电阻率的可能性，其中器件性能可能显着地取决于电阻率比寄生电容。

13. 发明申请

US20090181537A1 SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICAL CONNECTION AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：包含电气连接的半导体结构及其形成方法
公开(公告)号：US20090181537A1
公开(公告)日：2009-07-16
申请号：US12411873
申请日：2009-03-26
申请人： ROBERT SEIDEL , Ralf Richter , Frank Feustel
发明人： ROBERT SEIDEL , Ralf Richter , Frank Feustel
IPC分类号： H01L21/768
CPC分类号： H01L21/7684 , H01L21/7682 , H01L21/76829 , H01L21/76885
摘要： A method of forming a semiconductor structure comprises providing a substrate comprising a layer of a first material. A protection layer is formed over the layer of first material. At least one opening is formed in the layer of first material and the protection layer. A layer of a second material is formed over the layer of first material and the protection layer to fill the opening with the second material. A planarization process is performed to remove portions of the layer of second material outside the opening. At least a portion of the protection layer is not removed during the planarization process. An etching process is performed to remove the portions of the protection layer which were not removed during the planarization process.
摘要翻译：一种形成半导体结构的方法包括提供包括第一材料层的衬底。在第一材料层上形成保护层。在第一材料层和保护层中形成至少一个开口。在第一材料层上形成第二材料层，并且保护层用第二材料填充开口。执行平面化处理以去除开口外部的第二材料层的部分。在平坦化处理期间，保护层的至少一部分不被去除。执行蚀刻处理以去除在平坦化处理期间未被去除的保护层的部分。

14. 发明授权

US08163594B2 Semiconductor device comprising a carbon-based material for through hole vias 有权
标题翻译：包括用于通孔过孔的碳基材料的半导体器件
公开(公告)号：US08163594B2
公开(公告)日：2012-04-24
申请号：US12505098
申请日：2009-07-17
申请人： Robert Seidel , Frank Feustel , Ralf Richter
发明人： Robert Seidel , Frank Feustel , Ralf Richter
IPC分类号： H01L21/31
CPC分类号： H01L21/76898 , H01L23/53276 , H01L25/0657 , H01L25/50 , H01L2224/0554 , H01L2224/05573 , H01L2224/056 , H01L2224/13025 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/1305 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrical performance compared to doped semiconductor materials and the like. Thus, in some illustrative embodiments, the through hole vias may be formed prior to any process steps used for forming critical circuit elements, thereby substantially avoiding any interference of the through hole via structure with a device level of the corresponding semiconductor device. Consequently, highly efficient three-dimensional integration schemes may be realized.
摘要翻译：在半导体器件中，可以基于含碳材料形成延伸穿过器件的衬底的通孔，从而与高温工艺相比具有优异的兼容性，同时与掺杂的半导体材料相比提供优异的电性能，类似。因此，在一些说明性实施例中，通孔过孔可以在用于形成关键电路元件的任何工艺步骤之前形成，从而基本上避免了通孔通孔结构与对应的半导体器件的器件级别的任何干扰。因此，可以实现高效率的三维集成方案。

15. 发明授权

US07875514B2 Technique for compensating for a difference in deposition behavior in an interlayer dielectric material 有权
标题翻译：补偿层间电介质材料沉积行为差异的技术
公开(公告)号：US07875514B2
公开(公告)日：2011-01-25
申请号：US12841313
申请日：2010-07-22
申请人： Ralf Richter , Robert Seidel , Carsten Peters
发明人： Ralf Richter , Robert Seidel , Carsten Peters
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76816 , H01L21/76819 , H01L21/76829 , H01L21/76832 , H01L29/7843
摘要： By selectively providing a buffer layer having an appropriate thickness, height differences occurring during the deposition of an SACVD silicon dioxide may be reduced during the formation of an interlayer dielectric stack of advanced semiconductor devices. The buffer material may be selectively provided after the deposition of contact etch stop layers of both types of internal stress or may be provided after the deposition of one type of dielectric material and may be used during the subsequent patterning of the other type of dielectric stop material as an efficient etch stop layer.
摘要翻译：通过选择性地提供具有适当厚度的缓冲层，在形成先进的半导体器件的层间电介质叠层的过程中，可以减少沉积SACVD二氧化硅期间出现的高度差异。可以在沉积两种类型的内部应力的接触蚀刻停止层之后选择性地提供缓冲材料，或者可以在沉积一种类型的电介质材料之后提供缓冲材料，并且可以在随后的其它类型的电介质停止材料的图案化期间使用缓冲材料作为有效的蚀刻停止层。

16. 发明申请

US20080182409A1 METHOD OF FORMING A METAL LAYER OVER A PATTERNED DIELECTRIC BY ELECTROLESS DEPOSITION USING A SELECTIVELY PROVIDED ACTIVATION LAYER 审中-公开
标题翻译：使用选择性激活层通过电沉积形成图形电介质的金属层的方法
公开(公告)号：US20080182409A1
公开(公告)日：2008-07-31
申请号：US11782987
申请日：2007-07-25
申请人： Robert Seidel , Axel Preusse , Ralf Richter
发明人： Robert Seidel , Axel Preusse , Ralf Richter
IPC分类号： H01L21/445
CPC分类号： H01L21/76879 , H01L21/76843 , H01L21/76844 , H01L21/76849 , H01L21/76859 , H01L21/76865 , H01L21/76867 , H01L21/76874
摘要： By forming an activation/nucleation layer selectively at a bottom of an opening, efficient electroless deposition techniques may be used for forming contacts, vias and trenches of advanced semiconductor devices. By selectively providing the activation material, a self-aligned bottom-to-top fill behavior may be obtained.
摘要翻译：通过在开口的底部选择性地形成活化/成核层，可以使用有效的无电沉积技术来形成先进的半导体器件的触点，通路和沟槽。通过选择性地提供活化材料，可以获得自对准的底对顶填充行为。

17. 发明授权

US09034744B2 Replacement gate approach for high-k metal gate stacks by avoiding a polishing process for exposing the placeholder material 有权
标题翻译：通过避免用于暴露占位符材料的抛光工艺，用于高k金属栅极堆叠的替代栅极方法
公开(公告)号：US09034744B2
公开(公告)日：2015-05-19
申请号：US12942200
申请日：2010-11-09
申请人： Ralf Richter , Jens Heinrich , Andy Wei
发明人： Ralf Richter , Jens Heinrich , Andy Wei
IPC分类号： H01L29/772 , H01L21/8238 , H01L21/768 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823842 , H01L21/76819 , H01L21/823807 , H01L29/66545 , H01L29/66583 , H01L29/7833 , H01L29/7843
摘要： In a replacement gate approach, the exposure of the placeholder material of the gate electrode structures may be accomplished on the basis of an etch process, thereby avoiding the introduction of process-related non-uniformities, which are typically associated with a complex polishing process for exposing the top surface of the placeholder material. In some illustrative embodiments, the placeholder material may be exposed by an etch process based on a sacrificial mask material.
摘要翻译：在替代栅极方法中，栅极电极结构的占位符材料的暴露可以基于蚀刻工艺来实现，从而避免引入与工艺相关的非均匀性，这通常与复杂的抛光工艺相关暴露占位符材料的顶面。在一些说明性实施例中，占位符材料可以通过基于牺牲掩模材料的蚀刻工艺曝光。

18. 发明授权

US08951907B2 Semiconductor devices having through-contacts and related fabrication methods 有权
标题翻译：具有通孔和相关制造方法的半导体器件
公开(公告)号：US08951907B2
公开(公告)日：2015-02-10
申请号：US12968068
申请日：2010-12-14
申请人： Ralf Richter , Jens Heinrich , Holger Schuehrer
发明人： Ralf Richter , Jens Heinrich , Holger Schuehrer
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/285 , H01L23/485
CPC分类号： H01L21/76808 , H01L21/28512 , H01L21/76802 , H01L21/76897 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Apparatus for semiconductor device structures and related fabrication methods are provided. One method for fabricating a semiconductor device structure involves forming a layer of dielectric material overlying a doped region formed in a semiconductor substrate adjacent to a gate structure and forming a conductive contact in the layer of dielectric material. The conductive contact overlies and electrically connects to the doped region. The method continues by forming a second layer of dielectric material overlying the conductive contact, forming a voided region in the second layer overlying the conductive contact, forming a third layer of dielectric material overlying the voided region, and forming another voided region in the third layer overlying at least a portion of the voided region in the second layer. The method continues by forming a conductive material that fills both voided regions to contact the conductive contact.
摘要翻译：提供了半导体器件结构和相关制造方法的装置。一种用于制造半导体器件结构的方法包括形成覆盖在与栅极结构相邻的半导体衬底中形成的掺杂区域的介电材料层，并在该介电材料层中形成导电接触。导电接触覆盖并电连接到掺杂区域。该方法继续通过形成覆盖导电接触的第二层介电材料，在覆盖导电接触的第二层中形成空隙区域，形成覆盖空隙区域的第三层电介质材料，以及在第三层中形成另一个空隙区域覆盖第二层中的空隙区域的至少一部分。该方法通过形成填充两个空隙区域以接触导电触点的导电材料而继续。

19. 发明授权

US08697584B2 Enhanced transistor performance of N-channel transistors by using an additional layer above a dual stress liner in a semiconductor device 有权
标题翻译：通过在半导体器件中的双应力衬垫上方使用附加层来增强N沟道晶体管的晶体管性能
公开(公告)号：US08697584B2
公开(公告)日：2014-04-15
申请号：US12017175
申请日：2008-01-21
申请人： Ralf Richter , Andy Wei , Roman Boschke
发明人： Ralf Richter , Andy Wei , Roman Boschke
IPC分类号： H01L21/31
CPC分类号： H01L21/823807 , H01L29/7843
摘要： By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor.
摘要翻译：通过在构成不同固有应力的介电衬垫的图案之后形成诸如氮化硅的附加电介质材料，可以获得N沟道晶体管的性能的显着提高，同时基本上不会导致P沟道晶体管的性能损失。

20. 发明申请

US20140048912A1 COMPRESSIVE STRESS TRANSFER IN AN INTERLAYER DIELECTRIC OF A SEMICONDUCTOR DEVICE BY PROVIDING A BI-LAYER OF SUPERIOR ADHESION AND INTERNAL STRESS 有权
标题翻译：通过提供超级粘合和内应力的双层来在半导体器件的中间层电介质中的压应力传递
公开(公告)号：US20140048912A1
公开(公告)日：2014-02-20
申请号：US13588460
申请日：2012-08-17
申请人： Joerg Hohage , Hartmut Ruelke , Ralf Richter
发明人： Joerg Hohage , Hartmut Ruelke , Ralf Richter
IPC分类号： H01L21/31 , H01L29/06
CPC分类号： H01L21/76832 , C23C16/345 , C23C16/45523 , H01L21/0217 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/76834 , H01L21/823807 , H01L29/665 , H01L29/7833 , H01L29/7843
摘要： The present disclosure provides manufacturing techniques and semiconductor devices in which performance of P-channel transistors may be enhanced on the basis of a stress mechanism that involves the deposition of a dielectric bi-layer system. Contrary to conventional strategies, an additional pre-treatment may be performed prior to the deposition of an adhesion layer in a plasma-free process atmosphere, thereby enabling a reduced thickness of the adhesion layer and a higher internal stress level of the subsequent top layer.
摘要翻译：本公开提供了制造技术和半导体器件，其中可以基于涉及沉积介电双层系统的应力机制来增强P沟道晶体管的性能。与常规策略相反，可以在粘附层在无等离子体的工艺气氛中沉积之前进行另外的预处理，从而能够减小粘合层的厚度和随后的顶层的更高的内应力水平。

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