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11. 发明授权

US06362667B1 Output driver circuit 有权
公开(公告)号：US06362667B1
公开(公告)日：2002-03-26
申请号：US09789981
申请日：2001-02-20
申请人： Dirk Killat , Ordwin Haase , Heinz Werker
发明人： Dirk Killat , Ordwin Haase , Heinz Werker
IPC分类号： H03B100
摘要： The output driver circuit of an integrated circuit has several pairs of driver circuits and driver control circuits as well as a control device. Each pair of driver control circuit and driver circuit forms a driver stage. The driver stages are connected in series. Based on the input signal of the output driver circuit, the control device switches the signal direction through the succession of driver stages in such a way that, at the time the output driver circuit is switched either on or off, the driver stages are switched in a time delayed manner, whereby current pulses on the feeding lines and disturbance voltages induced in inductive loads are reduced.

12. 发明授权

US5856762A Phase-locked loop with course providing damping and natural frequency independence 失效
标题翻译：锁相环路提供阻尼和自然频率独立性
公开(公告)号：US5856762A
公开(公告)日：1999-01-05
申请号：US898516
申请日：1997-07-22
申请人： Heinz Werker , Thomas Eichler , Dirk Scheideler
发明人： Heinz Werker , Thomas Eichler , Dirk Scheideler
IPC分类号： H03L7/087 , H03L7/095 , H03L7/10 , H03L7/107
CPC分类号： H03L7/087 , H03L7/095 , H03L7/10 , H03L2207/04 , Y10S331/02
摘要： A phase-locked loop includes a switched phase detector, a loop filter and an oscillator connected in series, as well as a device for technology compensation, in particular a course control device. An operating point is adjusted during a starting phase of the phase-locked loop through the use of the course control device in such a way that the damping and natural frequency of the phase-locked loop is independent of fluctuations in technology parameters.
摘要翻译：锁相环包括开关相位检测器，环路滤波器和串联连接的振荡器，以及用于技术补偿的装置，特别是课程控制装置。通过使用路线控制装置在锁相环的启动阶段调整工作点，使得锁相环的阻尼和固有频率与技术参数的波动无关。

13. 发明授权

US07622966B2 Switchable phase locked loop and method for the operation of a switchable phase locked loop 有权
标题翻译：可切换的锁相环和可切换锁相环的操作方法
公开(公告)号：US07622966B2
公开(公告)日：2009-11-24
申请号：US11751871
申请日：2007-05-22
申请人： Heinz Werker
发明人： Heinz Werker
IPC分类号： H03L7/06
CPC分类号： H03L7/22 , H03L7/0814 , H03L7/087 , H03L7/091 , H03L7/10
摘要： The invention relates to a phase locked loop or “PLL” (12) and a method for the operation of a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and can be switched over between a first clock signal (CKin1 or CKin2) and a second clock signal (CKin2 or CKin1) for use as the input clock signal of the PLL (12). According to the invention, for the clock signal (CKin1 or CKin2) currently being used to generate the output signal (CKout), a phase difference between this clock signal and the output signal (CKout) is determined and used for the control of the oscillator (DCO), whereas for the clock signal (CKin2 or CKin1) currently not being used to generate the output signal (CKout), its frequency difference with respect to the output signal (CKout) is determined and stored and continuously updated and provided for the control of the oscillator (DCO) after the switch-over to this clock signal previously not being used. The PLL output signal (CKout) can thus follow more quickly any switch-over-related frequency change of the clock signal being used.
摘要翻译：本发明涉及一种锁相环或“PLL”（12）和一种用于操作PLL（12）的方法，其中可控振荡器（DCO）产生输出信号（CKout），并且可以在第一时钟信号（CKin1或CKin2）和第二时钟信号（CKin2或CKin1），用作PLL（12）的输入时钟信号。根据本发明，对于当前用于产生输出信号（CKout）的时钟信号（CKin1或CKin2），该时钟信号和输出信号（CKout）之间的相位差被确定并用于振荡器的控制（DCO），而对于当前未被用于产生输出信号（CKout）的时钟信号（CKin2或CKin1），其相对于输出信号（CKout）的频率差被确定并存储并连续更新并提供给切换到此时钟信号之前的振荡器（DCO）的控制以前未被使用。因此，PLL输出信号（CKout）可以更快速地跟踪正在使用的时钟信号的任何切换相关的频率变化。

14. 发明授权

US06747495B1 Low jitter analog-digital locker loop with lock detection circuit 有权
标题翻译：具有锁定检测电路的低抖动模拟数字储物柜回路
公开(公告)号：US06747495B1
公开(公告)日：2004-06-08
申请号：US09889260
申请日：2002-01-03
申请人： Siegfried Hart , Heinz Werker
发明人： Siegfried Hart , Heinz Werker
IPC分类号： H03L706
CPC分类号： G06F1/00 , H03K5/13 , H03L7/06 , H03L7/087 , H03L7/093 , H03L7/095 , H03L7/099 , Y10S331/02
摘要： A digital phase detector compares the output clock signal of the oscillator with the reference clock signal, an analog phase detector, and a lock detection circuit connected to a digital phase detector and an analog phase detector for avoiding a phase quantization error. The lock detection circuit activates the analog phase detector to run simultaneously with a digital phase detector if the phase error is zero. The activated analog phase detector regulates the output clock signal of the digitally controllable oscillator in a continuously variable manner until the respective clock signal edges of the output clock signal and the reference clock signal are fully synchronous. The lock detection circuit deactivates the analog phase detector and continuously checks and regulates the digital phase detector until the phase error between the output clock signal and the reference clock signal is zero.
摘要翻译：数字相位检测器将振荡器的输出时钟信号与参考时钟信号，模拟相位检测器和连接到数字相位检测器和模拟相位检测器的锁定检测电路进行比较，以避免相位量化误差。如果相位误差为零，锁定检测电路激活模拟相位检测器与数字相位检测器同时运行。激活的模拟相位检测器以连续可变的方式调节数字可控振荡器的输出时钟信号，直到输出时钟信号和参考时钟信号的各个时钟信号边沿完全同步。锁定检测电路停用模拟相位检测器，并连续检查和调节数字相位检测器，直到输出时钟信号和参考时钟信号之间的相位误差为零。

15. 发明授权

US5103191A Circuit configuration for phase locking 失效
标题翻译：锁相电路配置
公开(公告)号：US5103191A
公开(公告)日：1992-04-07
申请号：US557600
申请日：1990-07-25
申请人： Heinz Werker
发明人： Heinz Werker
IPC分类号： H03D13/00 , H03L7/089
CPC分类号： H03D13/004 , H03L7/0891
摘要： A circuit configuration includes a controllable oscillator issuing an output signal. A phase detector is acted upon by a reference signal and by the output signal of the oscillator. A first charge pump is controllable by the phase detector and has an input connected to the phase detector and an output. A loop filter is connected between the first charge pump and the oscillator for triggering the oscillator. A second charge pump is connected parallel to the output of the first charge pump.
摘要翻译：电路配置包括发出输出信号的可控振荡器。相位检测器由参考信号和振荡器的输出信号作用。第一电荷泵由相位检测器控制，并具有连接到相位检测器和输出端的输入端。环路滤波器连接在第一电荷泵和振荡器之间，用于触发振荡器。第二电荷泵与第一电荷泵的输出端并联连接。

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