专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07791407B2 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权
标题翻译：使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术
公开(公告)号：US07791407B2
公开(公告)日：2010-09-07
申请号：US11388558
申请日：2006-03-24
申请人： Khurram Muhammad , Robert B. Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert B. Staszewski , Dirk Leipold
IPC分类号： H03K5/00
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译：改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

12. 发明授权

US07382200B2 Type-II all-digital phase-locked loop (PLL) 有权
标题翻译： II型全数字锁相环（PLL）
公开(公告)号：US07382200B2
公开(公告)日：2008-06-03
申请号：US11464420
申请日：2006-08-14
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03L7/00
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

13. 发明授权

US07218904B2 Removing close-in interferers through a feedback loop 有权
标题翻译：通过反馈回路消除紧密的干扰源
公开(公告)号：US07218904B2
公开(公告)日：2007-05-15
申请号：US10280156
申请日：2002-10-25
申请人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
IPC分类号： H04B1/06 , H03F1/26
CPC分类号： H04B1/28 , H04B1/1036
摘要： System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.
摘要翻译：通过反馈消除接近干扰的系统和方法。优选实施例包括耦合到直接RF无线电接收机（例如，无线电接收机800）的数字输出的干扰源预测器（例如，干扰源预测器840）。干扰源预测器预测干扰源的存在，并且通过使用电荷共享通过反馈电路（例如，反馈单元845）将信息反馈给采样单元（例如，采样单元805）。然后在采样单元中消除干扰源。另外，通过执行任意系数有限脉冲响应滤波器来增加和改变采样单元滤波器中的零数和位置。

14. 发明授权

US06924681B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US06924681B2
公开(公告)日：2005-08-02
申请号：US10154093
申请日：2002-05-22
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03F1/02 , H03F1/06 , H03F3/217 , H03K3/00 , H03K3/017 , H03K5/06 , H03K7/02 , H04B1/04
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

15. 发明授权

US06734741B2 Frequency synthesizer with digitally-controlled oscillator 有权
公开(公告)号：US06734741B2
公开(公告)日：2004-05-11
申请号：US10006607
申请日：2001-11-30
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
IPC分类号： H03L700
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0966 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/50 , H04L7/0029
摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.

16. 发明授权

US07463873B2 Wireless communications device having type-II all-digital phase-locked loop (PLL) 有权
标题翻译：具有II型全数字锁相环（PLL）的无线通信设备
公开(公告)号：US07463873B2
公开(公告)日：2008-12-09
申请号：US11122670
申请日：2005-05-04
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03L7/093
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115 ) and an integral loop gain block (integral loop gain block 1120 ). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the intergral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

17. 发明授权

US06791422B2 Frequency synthesizer with digitally-controlled oscillator 有权
标题翻译：具有数字控制振荡器的频率合成器
公开(公告)号：US06791422B2
公开(公告)日：2004-09-14
申请号：US10679792
申请日：2003-10-06
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad , Chih-Ming Hung
IPC分类号： H03L700
CPC分类号： H03C3/0975 , H03C3/0941 , H03C3/095 , H03C3/0958 , H03C3/0966 , H03K19/0016 , H03L7/085 , H03L7/087 , H03L7/091 , H03L7/093 , H03L7/099 , H03L7/16 , H03L2207/50 , H04L7/0029
摘要： A transmitter (10) based on a frequency synthesizer includes an LC tank (12) of a digitally controlled oscillator (DCO) with various arrays of capacitors. The LC tank 12 is divided into two major groups that reflect two general operational modes: acquisition and tracking. The first group (process/voltage/temperature and acquisition) approximately sets the desired center frequency of oscillation initially, while the second group (integer and fractional tracking) precisely controls the oscillating frequency during the actual operation. For highly accurate outputs, dynamic element matching (DEM) is used in the integer tracking controller to reduce non-linearities caused by non-uniform capacitor values. Also, a preferred range of the integer tracking capacitor array may be used for modulation after the selected channel has been acquired. A digital sigma-delta modulator circuit (50) drives a capacitor array (14d) in response to the fractional bits of the error word. On mode switches, the accumulated error is recalculated to a phase restart value to prevent perturbations.
摘要翻译：基于频率合成器的发射机（10）包括具有各种电容器阵列的数字控制振荡器（DCO）的LC箱（12）。液相色谱箱12分为反映两种一般操作模式的两个主要组：采集和跟踪。第一组（过程/电压/温度和采集）最初初始化设置所需的中心振荡频率，而第二组（整数和分数跟踪）在实际操作期间精确地控制振荡频率。对于高精度输出，在整数跟踪控制器中使用动态元件匹配（DEM）来减少由非均匀电容值引起的非线性。此外，在获取所选择的信道之后，整数跟踪电容器阵列的优选范围可以用于调制。数字Σ-Δ调制器电路（50）响应错误字的分数位驱动电容器阵列（14d）。在模式开关上，累加误差被重新计算到相位重启值，以防止扰动。

18. 发明授权

US07145399B2 Type-II all-digital phase-locked loop (PLL) 有权
标题翻译： II型全数字锁相环（PLL）
公开(公告)号：US07145399B2
公开(公告)日：2006-12-05
申请号：US10464957
申请日：2003-06-19
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03D3/24
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

19. 发明授权

US07647192B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
标题翻译：通过在时间和空间上改变抽取比例，在抽取结构中主动去除混叠频率
公开(公告)号：US07647192B2
公开(公告)日：2010-01-12
申请号：US10924297
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
摘要翻译：当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。不同的抽取率导致不同的频率混叠成所需的频带。具有电容器组811和812的电流模式采样混频器800能够以不同的抽取率对能够集成和抽取RF电流的数字控制单元820进行控制，能够以不同的抽取率来测量频谱。然后分析测量的频谱以检测混叠到期望频带中的干扰源的存在。然后可以消除或避免干扰源。

20. 发明授权

US07466777B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
标题翻译：通过在时间和空间上改变抽取比例，在抽取结构中主动去除混叠频率
公开(公告)号：US07466777B2
公开(公告)日：2008-12-16
申请号：US10924159
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： H03D1/04
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
摘要翻译：当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。不同的抽取率导致不同的频率混叠成所需的频带。具有电容器组811和812的电流模式采样混频器800能够以不同的抽取率对能够集成和抽取RF电流的数字控制单元820进行控制，能够以不同的抽取率来测量频谱。然后分析测量的频谱以检测混叠到期望频带中的干扰源的存在。然后可以消除或避免干扰源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式