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11. 发明申请

US20070262397A1 Nanoscale Fet 有权
标题翻译：纳米级食物
公开(公告)号：US20070262397A1
公开(公告)日：2007-11-15
申请号：US11632738
申请日：2005-07-12
申请人： Radu Surdeanu , Prabhat Agarwal , Abraham Balkenende , Erik Bakkers
发明人： Radu Surdeanu , Prabhat Agarwal , Abraham Balkenende , Erik Bakkers
IPC分类号： H01L29/775 , H01L21/336
CPC分类号： H01L29/78 , B82Y10/00 , B82Y40/00 , H01L29/0665 , H01L29/0673 , H01L29/20 , H01L29/76 , Y10S438/962 , Y10S977/762 , Y10S977/818 , Y10S977/938
摘要： A transistor device is formed of a continuous linear nanostructure having a source region, a drain region and a channel region between the source and drain regions. The source (20) and drain (26) regions are formed of nanowire ania the channel region (24) is in the form of a nanotube. An insulated gate (32) is provided adjacent to the channel region (24) for controlling conduction i ni the channel region between the source and drain regions.
摘要翻译：晶体管器件由具有源极区，漏极区和源极和漏极区之间的沟道区的连续线性纳米结构形成。源极（20）和漏极（26）区域由纳米线形成，沟道区域（24）呈纳米管形式。绝缘栅极（32）设置成邻近沟道区（24），用于控制源极和漏极区之间的沟道区。

12. 发明授权

US09231201B2 Electric device with a layer of conductive material contacted by nanowires 有权
标题翻译：具有与纳米线接触的导电材料层的电气装置
公开(公告)号：US09231201B2
公开(公告)日：2016-01-05
申请号：US11631212
申请日：2005-06-28
申请人： Robertus Theodorus Fransiscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
发明人： Robertus Theodorus Fransiscus Van Schaijk , Prabhat Agarwal , Erik Petrus Antonius Maria Bakkers , Martijn Henri Richard Lankhorst , Michiel Jos Van Duuren , Abraham Rudolf Balkenende , Louis Felix Feiner , Pierre Hermanus Woerlee
IPC分类号： H01L47/00 , H01L45/00 , B82Y10/00 , G11C13/02 , H01L21/285 , H01L21/768 , H01L27/24 , G11C13/00
CPC分类号： H01L45/1273 , B82Y10/00 , G11C13/0004 , G11C13/025 , G11C2213/81 , H01L21/28525 , H01L21/76879 , H01L27/2409 , H01L27/2436 , H01L27/2472 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/148 , H01L45/16
摘要： The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
摘要翻译：根据本发明的电子设备（100）包括存储材料的层（107），其具有可在第一值和第二值之间切换的电阻率。记忆材料可以是相变材料。电气设备（100）还包括电连接电子设备的第一端子（172）和存储器材料层（107）的一组纳米线（NW），从而能够经由纳米线传导来自第一端子的电流（NW）和存储器材料层（107）连接到电气设备的第二端子（272）。每个纳米线（NW）在相应的接触区域中电接触存储器材料的层（107）。所有接触区域基本相同。根据本发明的方法适用于制造根据本发明的电子设备（100）。

13. 发明授权

US07759650B2 Implementation of avalanche photo diodes in (Bi)CMOS processes 有权
标题翻译：（Bi）CMOS工艺中雪崩光电二极管的实现
公开(公告)号：US07759650B2
公开(公告)日：2010-07-20
申请号：US12298206
申请日：2007-04-10
申请人： Anco Heringa , Thomas Frach , Prabhat Agarwal
发明人： Anco Heringa , Thomas Frach , Prabhat Agarwal
IPC分类号： G01T1/24
CPC分类号： H01L31/115 , H01L27/1446 , H01L31/107 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A radiation detector (46) includes a semiconductor layer(s) (12) formed on a substrate (14) and a scintillator (30) formed on the semiconductor layer(s) (12). The semiconductor layer(s) (12) includes an n-doped region (16) disposed adjacent to the substrate (14), and a p-doped region (18) disposed adjacent to the n-doped region (16). A trench (20) is formed within the semiconductor layer(s) (12) and around the p-doped region (18) and is filled with a material (22) that reduces pn junction curvature at the edges of the pn junction, which reduces breakdown at the edges. The scintillator (30) is disposed over and optically coupled to the p-doped regions (18). The radiation detector (46) further includes at least one conductive electrode (24) that electrically contacts the n-doped region.
摘要翻译：辐射检测器（46）包括形成在衬底（14）上的半导体层（12）和形成在半导体层（12）上的闪烁体（30）。半导体层（12）包括邻近衬底（14）设置的n掺杂区域（16）和邻近于n掺杂区域（16）设置的p掺杂区域（18）。沟槽（20）形成在半导体层（12）内并且围绕p掺杂区域（18）并且填充有减小pn结边缘处的pn结曲率的材料（22），其中减少边缘的破坏。闪烁体（30）设置在p掺杂区域（18）上并且光耦合到p掺杂区域（18）。辐射检测器（46）还包括与n掺杂区域电接触的至少一个导电电极（24）。

14. 发明授权

US07709923B2 Metal-base nanowire transistor 失效
标题翻译：金属基纳米线晶体管
公开(公告)号：US07709923B2
公开(公告)日：2010-05-04
申请号：US12093790
申请日：2006-10-29
申请人： Prabhat Agarwal , Godefridus A. M. Hurkx
发明人： Prabhat Agarwal , Godefridus A. M. Hurkx
IPC分类号： H01L27/095
CPC分类号： H01L29/7606 , B82Y10/00 , H01L29/0665 , H01L29/0673 , Y10S977/936
摘要： A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).
摘要翻译：建议使用金属晶体管。晶体管包括用于控制第一和第二电极之间的电流的第一和第二电极（2,6）和基极（6）。第一电极（2）由半导体材料制成。基极（3）是沉积在形成第一电极的半导体材料的顶部上的金属层。根据本发明，第二电极由与基极（3）电接触的半导体纳米线（6）形成。

15. 发明申请

US20080258182A1 Bicmos Compatible Jfet Device and Method of Manufacturing Same 审中-公开
标题翻译： Bicmos兼容Jfet设备及其制造方法相同
公开(公告)号：US20080258182A1
公开(公告)日：2008-10-23
申请号：US11577311
申请日：2005-10-13
申请人： Prabhat Agarwal , Jan W. Slotboom , Wibo Van Noort
发明人： Prabhat Agarwal , Jan W. Slotboom , Wibo Van Noort
IPC分类号： H01L29/808 , H01L21/8232 , H01L21/337
CPC分类号： H01L27/098 , H01L21/8248 , H01L27/0623
摘要： A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.
摘要翻译：一种BiCMOS兼容的JFET器件，包括以与用于形成发射极外扩散的相同的工艺形成的源极和漏极区域（17,18），或者垂直双极器件，其中形成发光极帽的半导体层双极器件形成JFET器件的沟道（16），并且形成双极器件的本征基极区域的材料层（即，基极外延堆叠）形成JFET器件的本征栅极区域（14）。结果，可以实现JFET器件到标准BiCMOS工艺的集成，而不需要任何额外的掩模或其他处理步骤。

16. 发明申请

US20080203434A1 Semiconductor Device with a Bipolar Transistor and Method of Manufacturing Such a Device 有权
标题翻译：具有双极晶体管的半导体器件及其制造方法
公开(公告)号：US20080203434A1
公开(公告)日：2008-08-28
申请号：US12088719
申请日：2006-09-22
申请人： Philippe Meunier-Beillard , Raymond James Duffy , Prabhat Agarwal , Godfridus Adrianus Maria Hurkx
发明人： Philippe Meunier-Beillard , Raymond James Duffy , Prabhat Agarwal , Godfridus Adrianus Maria Hurkx
IPC分类号： H01L29/737 , H01L21/331
CPC分类号： H01L29/7378 , H01L29/0817 , H01L29/66242
摘要： The invention relates to a semiconductor device (10) with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region (2) comprises a mixed crystal of silicon and germanium, the base region (2) is separated from the emitter region by an intermediate region (22) of silicon having a doping concentration which is lower than the doping concentration of the emitter region (1) and with a thickness smaller than the thickness of the emitter region (1) and the emitter region (1) comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region (1) remote from the intermediate region (22). According to the invention, the sub-region comprising the mixed crystal of silicon and germanium extend substantially through the whole emitter region (1) up to the interlace with the intermediate region (22) and the doping atoms of the emitter region (1) are arsenic atoms. Such a device has a very steep n-type doping profile (50) and a very steep p-type doping profile (20) at or within the intermediate region (22) and thus excellent high-frequency behavior with a high cut-off frequency (fr). Preferably the emitter region (1) is doped with an arsenic implantation (I) in its upper half, the final doping profile being formed after an RTA. The invention also comprises a method of manufacturing a device (10) according to the invention.
摘要翻译：本发明涉及一种具有衬底和硅半导体本体的半导体器件（10），其包括具有发射极区（1），基极区（2）和集电极区（3）的双极晶体管，所述发射极区分别为N 通过提供合适的掺杂原子，P型导电性和N型导电性，其中基区（2）包括硅和锗的混合晶体，基极区（2）与发射极分离通过具有低于发射极区域（1）的掺杂浓度的掺杂浓度并且具有小于发射极区域（1）和发射极区域（1）的厚度的厚度的硅的中间区域（22）包括位于远离中间区域（22）的发射极区域（1）侧的硅和锗的混合晶体的子区域。根据本发明，包括硅和锗的混合晶体的子区域基本上延伸穿过整个发射极区域（1）直到与中间区域（22）交错，并且发射极区域（1）的掺杂原子是砷原子这种器件在中间区域（22）处或中间区域（22）内具有非常陡峭的n型掺杂分布（50）和非常陡的p型掺杂分布（20），因此具有高截止频率的极好的高频特性（fr）。优选地，发射极区域（1）在其上半部分掺杂有砷注入（I），最后的掺杂分布在RTA之后形成。本发明还包括一种制造根据本发明的装置（10）的方法。

17. 发明申请

US20080144355A1 Dielectric Antifuse for Electro-Thermally Programmable Device 有权
标题翻译：电热可编程器件介质防腐剂
公开(公告)号：US20080144355A1
公开(公告)日：2008-06-19
申请号：US11720320
申请日：2005-11-24
申请人： Hans M.B. Boeve , Karen Attenborough , Godefridus A.M. Hurkx , Prabhat Agarwal , Hendrik G.A. Huizing , Michael A.A. In'T Zandt , Jan W. Slotboom
发明人： Hans M.B. Boeve , Karen Attenborough , Godefridus A.M. Hurkx , Prabhat Agarwal , Hendrik G.A. Huizing , Michael A.A. In'T Zandt , Jan W. Slotboom
IPC分类号： G11C17/18 , G11C11/00 , H01L21/326 , H01L29/02
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.
摘要翻译：热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。这种吹制的反熔丝具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压来吹动电介质中的小孔，以形成小导电路径，用作编程材料的微小电加热器。由于目前由孔的限制，为了切换到高电阻状态必须被加热的材料的体积非常小。因此，编程功率可能很低。

18. 发明申请

US20070279091A1 Digital Voltage Level Shifter 审中-公开
标题翻译：数字电压电平变换器
公开(公告)号：US20070279091A1
公开(公告)日：2007-12-06
申请号：US11663406
申请日：2004-09-22
申请人： Mayank Goel , Prabhat Agarwal
发明人： Mayank Goel , Prabhat Agarwal
IPC分类号： H03K3/356
CPC分类号： H03K3/356147 , H03K17/102
摘要： A digital voltage level shifter for converting an input signal with a low voltage swing to an output signal with a high voltage swing comprises a first inverter stage for generating an inverted signal from an input signal, the inverted signal having a voltage swing between a core voltage and ground, and a second inverter stage for producing an anti-phase signal from the inverted input signal, the anti-phase signal having a voltage swing between the core voltage and ground. The first and second inverters each drive a respective thin gate NMOS transistor connected in cascode with a respective NMOS transistor. The sources of the first and second thin gate NMOS transistors are connected to ground. The gates of the NMOS transistors are connected to the output of the respective inverters through a respective capacitor and are referenced to the core voltage through a respective resistor. The drains of the NMOS transistors are connected to an output circuit to provide an output signal having a voltage higher than the core voltage.
摘要翻译：用于将具有低电压摆幅的输入信号转换为具有高电压摆幅的输出信号的数字电压电平移位器包括用于从输入信号产生反相信号的第一反相器级，反相信号具有在核心电压以及用于从反相输入信号产生反相信号的第二反相器级，反相信号在核心电压和地之间具有电压摆幅。第一和第二反相器各自驱动以共源共栅连接的相应的薄栅极NMOS晶体管与相应的NMOS晶体管。第一和第二薄栅NMOS晶体管的源极连接到地。 NMOS晶体管的栅极通过相应的电容器连接到各个反相器的输出，并且通过相应的电阻器参考核心电压。 NMOS晶体管的漏极连接到输出电路，以提供具有高于核心电压的电压的输出信号。

19. 发明授权

US07839209B2 Tunnel field effect transistor 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US07839209B2
公开(公告)日：2010-11-23
申请号：US12444140
申请日：2007-10-03
申请人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A. M. Hurkx , Radu Surdeanu , Gerben Doornbos
发明人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A. M. Hurkx , Radu Surdeanu , Gerben Doornbos
IPC分类号： H01L25/00
CPC分类号： H01L29/161 , H01L29/165 , H01L29/7391
摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
摘要翻译：隧道晶体管包括与漏扩散（6）相反的导电类型的源极扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。绝缘栅极（16）控制耗尽层的位置和厚度。该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

20. 发明授权

US07714292B2 Geiger mode avalanche photodiode 有权
标题翻译：盖革模式雪崩光电二极管
公开(公告)号：US07714292B2
公开(公告)日：2010-05-11
申请号：US12162999
申请日：2007-01-17
申请人： Prabhat Agarwal , Jan Sonsky , Lasse Juhana Kauppinen
发明人： Prabhat Agarwal , Jan Sonsky , Lasse Juhana Kauppinen
IPC分类号： G01T1/24
CPC分类号： H01L27/14658 , H01L27/1464 , H01L27/14683 , H01L31/107
摘要： A avalanche mode photodiode array (102) is fabricated using a silicon on insulator wafer and substrate transfer process. The array includes a plurality of photodiodes (100). The photodiodes (100) include an electrically insulative layer (206), a depletion region (204), and first (208) and second (210) doped regions. An interconnection layer (212) includes electrodes (214, 216) which provides electrical connections to the photodiodes. The photodiode array (102) is carried by a handle wafer (217).
摘要翻译：使用绝缘体上硅晶片和衬底转移工艺制造雪崩模式光电二极管阵列（102）。阵列包括多个光电二极管（100）。光电二极管（100）包括电绝缘层（206），耗尽区（204）以及第一（208）和第二（210）掺杂区。互连层（212）包括提供到光电二极管的电连接的电极（214,216）。光电二极管阵列（102）由处理晶片（217）承载。

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