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    • 11. 发明授权
    • Edge enhancement with background noise suppression in video image processing
    • 边缘增强与视频图像处理中的背景噪声抑制
    • US06441866B1
    • 2002-08-27
    • US09231932
    • 1999-01-14
    • Datong ChenHongli Yang
    • Datong ChenHongli Yang
    • H04N521
    • H04N5/208
    • In the field of imaging, various components may contribute to a loss in resolution at higher spatial frequencies, both horizontally and vertically. Higher spatial frequencies may occur at the edge of an image, where there may be a large transition in the signal output between adjacent pixels. To compensate, an edge enhancement method that produces overshoots in the transitions of the video image signal is used. One of the problems with the edge enhancement method is that the noise in the input signal may not be adequately suppressed. To suppress the background noise in the video image signal while still performing the desired edge enhancement function, biasing circuitry may be used to suppress the smaller transitions in the input signal. In particular, the biasing circuitry may be placed in the signal path between the output of a first delay line and the noninverting inputs of two of the signal amplifiers. In this manner, the smaller transitions in the signal which represent background noise may be suppressed, while the edges of the video image signal are still enhanced.
    • 在成像领域,各种组件可能会在较高空间频率(水平和垂直)上造成分辨率的损失。 在图像的边缘处可能出现较高的空间频率,其中在相邻像素之间的信号输出中可能存在大的跃迁。 为了补偿,使用在视频图像信号的转变中产生过冲的边缘增强方法。 边缘增强方法的一个问题是输入信号中的噪声可能不能被充分抑制。 为了在仍然执行期望的边缘增强功能的同时抑制视频图像信号中的背景噪声,可以使用偏置电路来抑制输入信号中较小的转变。 特别地,偏置电路可以放置在第一延迟线的输出和两个信号放大器的同相输入之间的信号路径中。 以这种方式,可以抑制表示背景噪声的信号中较小的转变,而视频图像信号的边缘仍然增强。
    • 12. 发明授权
    • High-voltage complementary bipolar and BiCMOS technology using double expitaxial growth
    • 高电压互补双极和BiCMOS技术采用双外延生长
    • US06365447B1
    • 2002-04-02
    • US09005786
    • 1998-01-12
    • Francois HèbertDatong ChenReda Razouk
    • Francois HèbertDatong ChenReda Razouk
    • H01L218238
    • H01L21/84H01L21/8249H01L27/1203
    • A method of making high voltage complementary bipolar and BiCMOS devices on a common substrate. The bipolar devices are vertical NPN and PNP transistors having the same structure. The fabrication process utilizes trench isolation and thus is scalable. The process uses two epitaxial silicon layers to form the high voltage NPN collector, with the PNP collector formed from a p-well diffused into the two epitaxial layers. The collector contact resistance is minimized by the use of sinker up/down structures formed at the interface of the two epitaxial layers. The process minimizes the thermal budget and therefore the up diffusion of the NPN and PNP buried layers. This maximizes the breakdown voltage at the collector-emitter junction for a given epitaxial thickness. The epitaxial layers may be doped as required depending upon the specifications for the high voltage NPN device. The process is compatible with the fabrication of low voltage devices, which can be formed by placing the sinker regions under the emitter region. The thicknesses of the two epitaxial layers may be adjusted as required depending upon the specifications for the low voltage devices.
    • 在公共衬底上制造高电压互补双极和BiCMOS器件的方法。 双极器件是具有相同结构的垂直NPN和PNP晶体管。 制造工艺利用沟槽隔离,因此是可扩展的。 该工艺使用两个外延硅层来形成高压NPN集电极,PNP集电极由扩散到两个外延层中的p阱形成。 通过使用在两个外延层的界面处形成的沉降片上/下结构来最小化集电极接触电阻。 该过程使热预算最小化,因此最小化NPN和PNP埋层的向上扩散。 对于给定的外延厚度,这使集电极 - 发射极结处的击穿电压最大化。 外延层可以根据需要掺杂,这取决于高压NPN器件的规格。 该工艺与低电压器件的制造兼容,这可以通过将沉降片区域放置在发射极区域下而形成。 根据低电压器件的规格,可以根据需要调整两个外延层的厚度。
    • 13. 发明授权
    • Fabrication of a total internal reflection optical switch with vertical
fluid fill-holes
    • 具有垂直流体填充孔的全内反射光学开关的制造
    • US6055344A
    • 2000-04-25
    • US025892
    • 1998-02-18
    • Julie E. FouquetPatricia A. BeckDatong Chen
    • Julie E. FouquetPatricia A. BeckDatong Chen
    • G02B26/08G02B6/35G02B26/02
    • G02B26/004G02B6/3538G02B6/3546G02B6/3576G02B6/3596Y10T29/49016
    • A method of fabricating a switching element or a matrix of switching elements includes providing a waveguide substrate having at least two waveguides that intersect at a trench such that optical coupling between the waveguides is dependent upon the presence or absence of an index-matching fluid at the intersection of the waveguides with the trench. Fluid is supplied to the trench via a fluid fill-hole that extends through a heater substrate in a direction that is generally perpendicular to a substrate surface on which at least one heater is fabricated. In the preferred embodiment, the fluid fill-hole is formed in a step of inductively coupled plasma (ICP) reactive ion etching (RIE). The waveguide substrate having at least two waveguides and the heater substrate having the heaters and the fill-hole are bonded together after the substrates are aligned such that the trench is in fluid communication with at least one fluid fill-hole and is in thermal communication with at least one heater. Optical fibers are then coupled to the waveguides. Preferably, a structurally weakened edge portion is formed during the ICP RIE step so that the edge portion can be removed after the two substrates are bonded, allowing uninhibited access of the optical fibers to the waveguides.
    • 制造开关元件或开关元件矩阵的方法包括提供具有至少两个在沟槽处相交的波导的波导基板,使得波导之间的光耦合取决于在该波导处的存在或不存在折射率匹配流体 波导与沟槽的交点。 流体通过流体填充孔被供应到沟槽,流体填充孔沿着大致垂直于其上制造至少一个加热器的基板表面的方向延伸穿过加热器基板。 在优选实施例中,在电感耦合等离子体(ICP)反应离子蚀刻(RIE)的步骤中形成流体填充孔。 具有至少两个波导的波导基板和具有加热器和填充孔的加热器基板在基板对准之后结合在一起,使得沟槽与至少一个流体填充孔流体连通并且与 至少一个加热器。 然后将光纤耦合到波导。 优选地,在ICP RIE步骤期间形成结构弱化的边缘部分,使得在两个基板接合之后可以去除边缘部分,允许光纤到波导的不受限制的访问。
    • 14. 发明授权
    • Active pixel with a pinned photodiode
    • 有源像素带有钉扎光电二极管
    • US5880495A
    • 1999-03-09
    • US4215
    • 1998-01-08
    • Datong Chen
    • Datong Chen
    • H01L27/146H01L31/062
    • H01L27/14643H01L27/14609
    • An active pixel for use in an imaging array and formed in a semiconductor substrate having a first conductivity type. The active pixel comprises: a pinned photodiode formed in the semiconductor substrate; a transfer well having a second conductivity type formed in the substrate, the transfer well being adjacent to the pinned photodiode; a transfer gate adjacent the transfer well, the transfer gate for controlling the flow of a signal charge from the pinned photodiode through the transfer well and under the transfer gate; and an output well adjacent the transfer gate for receiving the signal charge and routing the signal charge to output circuitry.
    • 用于成像阵列并形成在具有第一导电类型的半导体衬底中的有源像素。 有源像素包括:形成在半导体衬底中的钉扎光电二极管; 在衬底中形成具有第二导电类型的转移阱,所述转移阱邻近被钉扎的光电二极管; 与转移阱相邻的传输门,用于控制来自钉扎光电二极管的信号电荷通过传输阱并在传输门下方的传输门; 以及与传输门相邻的输出阱,用于接收信号电荷并将信号电荷路由到输出电路。
    • 17. 发明申请
    • SYNCHRONIZED SOLAR CONCENTRATOR ARRAY
    • 同步太阳能集中器阵列
    • US20090266354A1
    • 2009-10-29
    • US12303361
    • 2007-06-02
    • Datong Chen
    • Datong Chen
    • F24J2/38
    • F24S50/20F24S23/30F24S23/70Y02B10/20Y02E10/47
    • A solar energy collecting device includes a rotation axis to be mounted parallel to the earth's polar axis, a solar energy collector mounted for rotation around the rotation axis at a predetermined rotation speed, the solar energy collector defining a tilt angle with respect to the rotation axis, and a tilt angle adjustment mechanism for automatically and intermittently adjusting the tilt angle. Various configurations of the solar energy collector are possible, and the rotation speed may be one revolution per day or half a revolution per day depending on the solar energy collector configuration. Many drive modes are possible, including rotating continuously throughout a day or rotating during daylight hours and rotating backward or forward at night. The tilt angle adjustment mechanism includes a handle fixed to the solar energy collector and a tilt angle change guide.
    • 太阳能收集装置包括平行于地球极轴的旋转轴线,安装成以预定转速围绕旋转轴旋转的太阳能收集器,太阳能收集器限定相对于旋转轴线的倾斜角度 以及用于自动和间歇地调整倾斜角的倾斜角度调节机构。 太阳能收集器的各种构造是可能的,并且根据太阳能收集器配置,旋转速度可以是每天一转还是每天一转一半。 许多驱动模式是可能的,包括一天中连续旋转或在白天小时旋转,并在夜间向后或向前旋转。 倾斜角度调节机构包括固定于太阳能收集器的手柄和倾斜角度变化导向器。
    • 18. 发明授权
    • Optical cache memory
    • 光缓存存储器
    • US06917739B2
    • 2005-07-12
    • US10401827
    • 2003-03-27
    • Datong Chen
    • Datong Chen
    • G02F3/00G02B6/28G06E3/00G11C21/00H04B10/00H04Q11/00G02B6/42
    • G06E3/00G02B6/2861H04Q11/0005H04Q2011/002
    • An optical memory having an input port for receiving an input optical signal to be stored in the optical memory is disclosed. A portion of the optical signal is coupled to a storage loop for storing optical signals by a coupler that transfers a portion of the input optical signal to the storage loop. An optical signal stored in the storage loop is output by coupling a portion of that optical signal to a first external optical waveguide. The storage loop includes a semiconductor optical amplifier for amplifying the signals stored in the storage loop to compensate for losses incurred by those signals in traversing the storage loop. A plurality of such optical memories can be combined to form a larger memory that includes a reconditioning circuit that resets the amplitude of the optical signals to a value that depends on the amplitude of the optical signals.
    • 公开了具有用于接收要存储在光存储器中的输入光信号的输入端口的光存储器。 光信号的一部分耦合到存储环路,用于通过将输入光信号的一部分传送到存储环路的耦合器存储光信号。 通过将该光信号的一部分耦合到第一外部光波导来输出存储在存储环路中的光信号。 存储环路包括用于放大存储在存储环路中的信号的半导体光放大器,以补偿这些信号在穿过存储环路时引起的损耗。 可以组合多个这样的光存储器以形成更大的存储器,其包括将光信号的幅度重置为取决于光信号的幅度的值的修复电路。
    • 19. 发明授权
    • Optical switch incorporating stepped faceted mirrors
    • 光学开关结合了台阶面镜
    • US06842557B2
    • 2005-01-11
    • US10418669
    • 2003-04-18
    • Datong ChenJohn C. PhilippIan Hardcastle
    • Datong ChenJohn C. PhilippIan Hardcastle
    • G02B26/08G02B6/12G02B6/35G02B6/26
    • G02B6/352G02B6/3546G02B6/3578G02B2006/12104
    • An optical switch that includes optical paths organized into a set of M input optical paths and a set of N output optical paths, where at least one of M and N is greater than unity. The optical switch additionally includes a faceted mirror corresponding to each of the M input optical paths and including N facets and a faceted mirror corresponding to each of the N output optical paths and including M facets. Finally, the optical switch includes a moving mechanism coupled to each faceted mirror to step the faceted mirror linearly in a direction orthogonal to the optical paths to selectively align one of the facets of the faceted mirror with the one of the optical paths with which the faceted mirror is associated. The facets of each of the faceted mirror corresponding to one of the sets of optical paths, i.e., the set of input optical paths or the set of output optical paths, are preferably angled to reflect light towards a different one of the faceted mirrors corresponding to the other of the sets of optical paths, i.e., the set of output optical paths or the set of input optical paths, respectively.
    • 一种光学开关,其包括组织成一组M个输入光路的光路和一组N个输出光路,其中M和N中的至少一个大于1。 光开关还包括与M个输入光路中的每一个相对应的分面镜,并且包括N个刻面和与N个输出光路中的每一个相对应并包括M个刻面的刻面镜。 最后,光学开关包括耦合到每个刻面镜的移动机构,以在垂直于光路的方向上线性地平移成双面反射镜,以便选择性地对准分面反射镜的一个面与光刻面之一 镜子相关联。 对应于光路组中的一组,即输入光路组或输出光路组的每一个分面反射镜的小面最好是成角度的,以将光反射到对应于 光路组中的另一组,即输出光路组或输入光路组。
    • 20. 发明授权
    • APS soft reset circuit for reducing image lag
    • APS软复位电路,用于降低图像滞后
    • US06727946B1
    • 2004-04-27
    • US09461668
    • 1999-12-14
    • Tiemin ZhaoXinping HeQingwei ShanDatong Chen
    • Tiemin ZhaoXinping HeQingwei ShanDatong Chen
    • H04N314
    • H04N5/363H04N5/3698H04N5/374
    • An improved active pixel sensor soft reset circuit for reducing image lag while maintaining low reset kTC noise. The circuit pulls down the sensor potential to a sufficiently low level before the soft reset function is completed. The level to which the sensor potential is pulled is set between 0 and the critical potential at which the reset transistor will be on when the soft reset function begins. The timing of the pull down function is such that the sensor is stabilized at the low potential before the soft reset function completes. In one embodiment, the sensor potential is pulled down using a pull-down circuit, which may consist of a CMOS type inverter. In another embodiment, the sensor potential is pulled down by the bit line. Two ways in which the bit line may be pulled down are natural discharge, or by increasing the bias on the loading transistor. Two ways in which the bias on the loading transistor may be increased are a biasing circuit, or by using a pull-down transistor. The active pixel sensor may be implemented with any suitable sensor technology, such as photodiode, photogate, or pinned diode.
    • 一种改进的有源像素传感器软复位电路,用于在保持低复位kTC噪声的同时降低图像滞后。 在软复位功能完成之前,电路将传感器电位下降到足够低的水平。 将传感器电位拉到的电平设置在0和软复位功能开始时复位晶体管导通的临界电位。 下拉功能的定时使得传感器在软复位功能完成之前稳定在低电位。 在一个实施例中,使用可由CMOS型逆变器组成的下拉电路将传感器电位下拉。 在另一个实施例中,传感器电位被位线下拉。 可以将位线拉下的两种方法是自然放电,或通过增加负载晶体管上的偏置。 负载晶体管上的偏置可能增加的两种方式是偏置电路,或通过使用下拉晶体管。 有源像素传感器可以用任何合适的传感器技术来实现,例如光电二极管,光栅或固定二极管。