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11. 发明授权

US06916670B2 Electronic package repair process 失效
标题翻译：电子封装修复过程
公开(公告)号：US06916670B2
公开(公告)日：2005-07-12
申请号：US10358431
申请日：2003-02-04
申请人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
发明人： Jon A. Casey , James G. Balz , Michael Berger , Jerome Cohen , Charles Hendricks , Richard Indyk , Mark LaPlante , David C. Long , Lori A. Maiorino , Arthur G. Merryman , Glenn A. Pomerantz , Robert A. Rita , Krystyna W. Semkow , Patrick E. Spencer , Brian R. Sundlof , Richard P. Surprenant , Donald R. Wall , Thomas A. Wassick , Kathleen M. Wiley
IPC分类号： H05K3/46 , H01L21/48 , H01L23/12 , H01L23/498 , H05K1/03 , H05K3/00 , H05K3/22 , H01L21/00
CPC分类号： H05K3/225 , H01L21/4846 , H01L23/49811 , H01L2924/0002 , H01L2924/09701 , H01L2924/3011 , H05K1/0306 , H05K3/0029 , H05K3/4629 , H05K2203/173 , Y10T29/49124 , Y10T29/49135 , H01L2924/00
摘要： A multilayer ceramic repair process which provides a new electrical repair path to connect top surface vias. The repair path is established between a defective net and a redundant repair net contained within the multilayer ceramic substrate. The defective net and the repair net each terminate at surface vias of the substrate. A laser is used to form post fired circuitry on and in the substrate. This is followed by the electrical isolation of the defective net from the electrical repair structure and passivation of the electrical repair line.
摘要翻译：一种多层陶瓷修复工艺，提供了一种新的电气修复路径，以连接顶部表面通孔。修复路径是建立在有缺陷的网和包含在多层陶瓷基片内的冗余修复网之间。有缺陷的网和修复网各自终止在基板的表面通孔处。使用激光器在基板上和基板上形成点火电路。之后是有缺陷的网络与电气修复结构的电气隔离和电气修复线路的钝化。

12. 发明授权

US06823585B2 Method of selective plating on a substrate 失效
标题翻译：在基板上选择性镀覆的方法
公开(公告)号：US06823585B2
公开(公告)日：2004-11-30
申请号：US10249305
申请日：2003-03-28
申请人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
发明人： Mark J. LaPlante , Jon A. Casey , Thomas A. Wassick , David C. Long , Krystyna W. Semkow , Patrick E. Spencer , Robert A. Rita , Richard F. Indyk , Kathleen M. Wiley , Brian R. Sundlof , James Balz , Lori A. Maiorino , Donald R. Wall , Glenn A. Pomerantz
IPC分类号： H01R4300
CPC分类号： H05K3/242 , H05K1/0306 , H05K3/0035 , H05K3/048 , H05K3/184 , H05K3/225 , H05K2203/0191 , H05K2203/0264 , H05K2203/0574 , Y10T29/49117 , Y10T29/49126 , Y10T29/49128 , Y10T29/49155 , Y10T29/49156 , Y10T29/49158 , Y10T29/49163 , Y10T29/49165 , Y10T29/49171 , Y10T29/49172 , Y10T29/49721 , Y10T29/49732 , Y10T29/49737 , Y10T29/49746
摘要： A method and structure to form surface plating metallization on a substrate. Two layers of tape are applied to the surface of the substrate. A first path is cut through both layers of tape exposing the substrate surface. The first path connects at least one conductive via on the top surface of the substrate. A second path is cut through the second layer of tape exposing the first layer of tape. The second path is routed from the first path to an edge of the substrate A seed layer is deposited over the surface of the second layer of tape thereby creating a seeded plating path in the first path and a sacrificial seeded conduction path in the second path. Connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate creates a plated path on the surface of the substrate. The sacrificial path is removed when the tape is removed.
摘要翻译：在基板上形成表面电镀金属化的方法和结构。将两层胶带施加到基材的表面。通过暴露衬底表面的两层带切割第一路径。第一路径在衬底的顶表面上连接至少一个导电通孔。通过暴露第一层胶带的第二层胶带切割第二条路径。第二路径从第一路径路由到衬底的边缘。种子层沉积在第二层带的表面上，从而在第一路径中形成种子电镀路径，并在第二路径中形成牺牲种子传导路径。将牺牲种子传导路径连接到衬底边缘处的电镀电位在衬底的表面上产生电镀路径。去除胶带时，去除牺牲路径。

13. 发明授权

US09059292B2 Source and drain doping profile control employing carbon-doped semiconductor material 有权
标题翻译：使用碳掺杂半导体材料的源极和漏极掺杂分布控制
公开(公告)号：US09059292B2
公开(公告)日：2015-06-16
申请号：US13564862
申请日：2012-08-02
申请人： Viorel Ontalus , Pranita Kulkarni , Donald R. Wall , Zhengmao Zhu
发明人： Viorel Ontalus , Pranita Kulkarni , Donald R. Wall , Zhengmao Zhu
IPC分类号： H01L29/02 , H01L29/786 , H01L29/66 , H01L29/08 , H01L29/165 , H01L29/417 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/823412 , H01L29/0649 , H01L29/165 , H01L29/167 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/66628 , H01L29/66772 , H01L29/78 , H01L29/7834 , H01L29/78618 , H01L29/78687 , H01L2029/7858
摘要： Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor.
摘要翻译：碳掺杂半导体材料部分形成在与场效应晶体管的沟道连接的下面的半导体表面的子集上。碳掺杂半导体材料部分可以通过含碳半导体材料层的选择性外延或通过将碳原子浅入注入下面的半导体表面的表面部分来形成。碳掺杂的半导体材料部分可以作为层沉积，然后通过蚀刻进行图案化，或者可以在形成一次性掩模间隔物之后形成。在碳掺杂的半导体材料部分和下面的半导体表面的物理暴露的表面上形成凸起的源区和漏区。碳掺杂半导体材料部分将掺杂剂扩散部分局部延迟从升高的源极和漏极区域延伸到下面的半导体材料区域中，从而使得能够局部定制掺杂剂分布，以及改变场效应晶体管的器件参数。

14. 发明授权

US06601284B1 Composite brake drum and method for producing same 有权
标题翻译：复合制动鼓及其制造方法
公开(公告)号：US06601284B1
公开(公告)日：2003-08-05
申请号：US09639547
申请日：2000-08-16
申请人： Donald R. Wall
发明人： Donald R. Wall
IPC分类号： B21B146
CPC分类号： B22D19/00 , B22D25/00 , F16D65/10 , F16D2065/132 , F16D2065/1332 , F16D2069/0483 , F16D2069/0491 , F16D2200/0078 , F16D2250/00 , F16D2250/0092 , Y10T29/49988 , Y10T29/49991
摘要： A composite brake drum for use in a drum brake assembly includes a one-piece mounting flange and shell and a liner cast integrally in a shell portion thereof. The method for forming the composite brake drum of this invention includes the steps of: (a) providing a generally circular metal blank having an initial pilot hole inner diameter; (b) spin forming the metal blank to produce a one-piece brake drum component defining a center longitudinal axis and including a cylindrical shell having a squealer band which defines a squealer band outer diameter, a mounting flange extending radially inwardly from one end of the shell toward the center longitudinal axis, and an annular lip extending radially inwardly from an opposite end of the shell toward the center longitudinal axis, and wherein the shell, the flange, and the lip cooperate to define a cylindrical mold cavity; (c) subsequent to step (b), centrifugally casting a liner in situ within the mold cavity of the brake drum component to thereby produce the composite vehicle brake drum; and (d) subsequent to step (c), machining the initial pilot hole inner diameter to a final pilot hole inner diameter by locating off of the squealer band outer diameter.
摘要翻译：用于鼓式制动器组件的复合制动鼓包括一体式安装法兰和壳体以及一体地铸造在壳体部分中的衬套。本发明的复合制动鼓的形成方法包括以下步骤：（a）提供具有初始导向孔内径的大致圆形的金属坯料; （b）旋转形成金属坯件以制造限定中心纵向轴线的一体式制动鼓部件，并且包括具有限定鼓轮带外径的尖叫带的圆柱形壳体，从所述滚筒的一端径向向内延伸的安装凸缘壳体朝向中心纵向轴线，以及环形唇缘，其从壳体的相对端朝向中心纵向轴线径向向内延伸，并且其中壳体，凸缘和唇缘配合以限定圆柱形模腔; （c）在步骤（b）之后，在制动鼓部件的模腔内离心铸造衬套，从而产生复合车辆制动鼓; 和（d）在步骤（c）之后，通过定位离开尖叫带外径的方式将初始导向孔内径加工到最终引导孔内径。

15. 发明申请

US20140035000A1 Source and Drain Doping Profile Control Employing Carbon-Doped Semiconductor Material 有权
标题翻译：源和漏极掺杂曲线控制采用碳掺杂半导体材料
公开(公告)号：US20140035000A1
公开(公告)日：2014-02-06
申请号：US13564862
申请日：2012-08-02
申请人： Viorel Ontalus , Pranita Kulkarni , Donald R. Wall , Zhengmao Zhu
发明人： Viorel Ontalus , Pranita Kulkarni , Donald R. Wall , Zhengmao Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/823412 , H01L29/0649 , H01L29/165 , H01L29/167 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/66628 , H01L29/66772 , H01L29/78 , H01L29/7834 , H01L29/78618 , H01L29/78687 , H01L2029/7858
摘要： Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor.
摘要翻译：碳掺杂半导体材料部分形成在与场效应晶体管的沟道连接的下面的半导体表面的子集上。碳掺杂半导体材料部分可以通过含碳半导体材料层的选择性外延或通过将碳原子浅入注入下面的半导体表面的表面部分来形成。碳掺杂的半导体材料部分可以作为层沉积，然后通过蚀刻进行图案化，或者可以在形成一次性掩模间隔物之后形成。在碳掺杂的半导体材料部分和下面的半导体表面的物理暴露的表面上形成凸起的源区和漏区。碳掺杂半导体材料部分将掺杂剂扩散部分局部延迟从升高的源极和漏极区域延伸到下面的半导体材料区域中，从而使得能够局部定制掺杂剂分布，以及改变场效应晶体管的器件参数。

16. 发明授权

US6068912A Platible non-metallic filler material for metallurgical screening paste 失效
标题翻译：用于冶金筛分浆料的可拉伸非金属填料
公开(公告)号：US6068912A
公开(公告)日：2000-05-30
申请号：US71409
申请日：1998-05-01
申请人： Srinivasa S. N. Reddy , Donald R. Wall
发明人： Srinivasa S. N. Reddy , Donald R. Wall
IPC分类号： H05K1/09 , C04B41/52 , C04B41/89 , C12N15/34 , C23C16/06 , H01L23/498 , H05K1/03 , H05K1/11 , H05K3/24 , H05K3/40 , B32B3/00 , C04B35/46
CPC分类号： H05K3/246 , C04B41/009 , C04B41/52 , C04B41/89 , H01L23/49883 , H05K3/4061 , C04B2111/00844 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K1/113 , H05K2201/0317 , H05K2201/0347 , H05K3/245 , Y10T428/24917 , Y10T428/24926 , Y10T428/265
摘要： A paste for one of a via and an external feature, such as a pad, tab, or line, of a ceramic substrate, includes at least one of titania and zirconia, and a filler material mixed with the at least one of titania and zirconia. Further, the via structure or external feature such as an input/output pad, tab, or line, includes a metallic plating thereover. A method of forming the via structure or the external feature on the ceramic substrate, includes steps of either depositing the paste in the via of the ceramic substrate or depositing the paste on the ceramic substrate, and depositing, by a dry process metallic plating, a metallic plating on the paste. The paste includes at least one of titania and zirconia for reducing residual stress without effecting the platability of the metallic plating.
摘要翻译：用于陶瓷基板的通孔和外部特征（例如垫，突片或线）之一的糊料包括二氧化钛和氧化锆中的至少一种，以及与二氧化钛和氧化锆中的至少一种混合的填充材料。此外，通孔结构或诸如输入/输出焊盘，突片或线的外部特征包括其上的金属电镀。在陶瓷基板上形成通孔结构或外部特征的方法包括以下步骤：将糊料沉积在陶瓷基板的通孔中或将该糊料沉积在陶瓷基板上，并通过干法金属镀层沉积金属电镀在糊状物上。糊料包括二氧化钛和氧化锆中的至少一种，用于降低残余应力而不影响金属镀层的镀层。

17. 发明授权

US5782324A Composite brake drum and method for producing same 失效
标题翻译：复合制动鼓及其制造方法
公开(公告)号：US5782324A
公开(公告)日：1998-07-21
申请号：US769196
申请日：1996-12-18
申请人： Donald R. Wall
发明人： Donald R. Wall
IPC分类号： B22D19/00 , B22D25/00 , F16D65/10 , F16D69/04
CPC分类号： B22D19/00 , B22D25/00 , F16D65/10 , F16D2065/132 , F16D2065/1332 , F16D2069/0483 , F16D2069/0491 , F16D2200/0078 , F16D2250/00 , F16D2250/0092 , Y10T29/49988 , Y10T29/49991
摘要： A composite brake drum for use in a drum brake assembly includes a one-piece mounting flange and shell and a liner cast integrally in a shell portion thereof. The method for forming the composite brake drum of this invention includes the steps of: (a) providing a generally flat sheet of a first material; (b) forming the flat sheet into a generally flat circular blank; (c) subjecting to the blank to a series of metal forming operations to produce a one piece mounting flange and shell; and (d) casting a liner formed from a second material within the one-piece mounting flange and shell to thereby produce the composite brake drum.
摘要翻译：用于鼓式制动器组件的复合制动鼓包括一体式安装法兰和壳体以及一体地铸造在壳体部分中的衬套。本发明的复合制动鼓的形成方法包括以下步骤：（a）提供大致平坦的第一材料片; （b）将平板形成为大致平坦的圆形坯料; （c）对坯料进行一系列的金属成型操作以制造一件安装法兰和外壳; 和（d）在一体式安装法兰和壳体内铸造由第二材料形成的衬垫，从而产生复合制动鼓。

18. 发明申请

US20110230030A1 STRAIN-PRESERVING ION IMPLANTATION METHODS 失效
标题翻译：应变保留离子植入方法
公开(公告)号：US20110230030A1
公开(公告)日：2011-09-22
申请号：US12724608
申请日：2010-03-16
申请人： Joel P. de Souza , Masafumi Hamaguchi , Ahmet S. Ozcan , Devendra K. Sadana , Katherine L. Saenger , Donald R. Wall
发明人： Joel P. de Souza , Masafumi Hamaguchi , Ahmet S. Ozcan , Devendra K. Sadana , Katherine L. Saenger , Donald R. Wall
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/324 , H01L29/165 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.
摘要翻译：具有与半导体衬底的矩阵不同的组成的嵌入式外延半导体部分与半导体衬底的矩阵形成晶格失配和外延对准。随后离子注入步骤的温度根据离子注入工艺的非晶化或非非晶化性质进行操作。对于非非晶化离子注入工艺，离子注入处理步骤在升高的温度，即大于标称室温范围的温度下进行。对于非晶化离子注入工艺，离子注入处理步骤在标称室温范围或低于标称室温范围的温度下进行。通过操纵离子注入的温度，使应变半导体合金材料中的应变损失最小化。

19. 发明授权

US06565917B1 Method of forming features on a ceramic substrate using platible pastes 有权
标题翻译：在陶瓷基板上使用可压焊膏形成特征的方法
公开(公告)号：US06565917B1
公开(公告)日：2003-05-20
申请号：US09525472
申请日：2000-03-15
申请人： Srinivasa S. N. Reddy , Donald R. Wall
发明人： Srinivasa S. N. Reddy , Donald R. Wall
IPC分类号： B05D512
CPC分类号： H05K3/246 , C04B41/009 , C04B41/52 , C04B41/89 , C04B2111/00844 , H01L23/49883 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K1/113 , H05K3/245 , H05K3/4061 , H05K2201/0317 , H05K2201/0347 , Y10T428/24917 , Y10T428/24926 , Y10T428/265 , C04B41/4539 , C04B41/4572 , C04B41/5031 , C04B41/5041 , C04B41/5042 , C04B41/5144 , C04B35/00 , H01L2924/00
摘要： A paste for one of a via and an external feature, such as a pad, tab, or line, of a ceramic substrate, includes at least one of titania and zirconia, and a filler material mixed with the at least one of titania and zirconia. Further, the via structure or external feature such as an input/output pad, tab, or line, includes a metallic plating thereover. A method of forming the via structure or the external feature on the ceramic substrate, includes steps of either depositing the paste in the via of the ceramic substrate or depositing the paste on the ceramic substrate, and depositing, by a dry process metallic plating, a metallic plating on the paste. The paste includes at least one of titania and zirconia for reducing residual stress without effecting the platability of the metallic plating.
摘要翻译：用于陶瓷基板的通孔和外部特征（例如垫，突片或线）之一的糊料包括二氧化钛和氧化锆中的至少一种，以及与二氧化钛和氧化锆中的至少一种混合的填充材料。此外，通孔结构或诸如输入/输出焊盘，突片或线的外部特征包括其上的金属电镀。在陶瓷基板上形成通孔结构或外部特征的方法包括以下步骤：将糊料沉积在陶瓷基板的通孔中或将该糊料沉积在陶瓷基板上，并通过干法金属镀层沉积金属电镀在糊状物上。糊料包括二氧化钛和氧化锆中的至少一种，用于降低残余应力而不影响金属镀层的镀层。

20. 发明授权

US08598006B2 Strain preserving ion implantation methods 失效
标题翻译：应变保留离子注入方法
公开(公告)号：US08598006B2
公开(公告)日：2013-12-03
申请号：US12724608
申请日：2010-03-16
申请人： Joel P. de Souza , Masafumi Hamaguchi , Ahmet S. Ozcan , Devendra K. Sadana , Katherine L. Saenger , Donald R. Wall
发明人： Joel P. de Souza , Masafumi Hamaguchi , Ahmet S. Ozcan , Devendra K. Sadana , Katherine L. Saenger , Donald R. Wall
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/324 , H01L29/165 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.
摘要翻译：具有与半导体衬底的矩阵不同的组成的嵌入式外延半导体部分与半导体衬底的矩阵形成晶格失配和外延对准。随后离子注入步骤的温度根据离子注入工艺的非晶化或非非晶化性质进行操作。对于非非晶化离子注入工艺，离子注入处理步骤在升高的温度，即大于标称室温范围的温度下进行。对于非晶化离子注入工艺，离子注入处理步骤在标称室温范围或低于标称室温范围的温度下进行。通过操纵离子注入的温度，使应变半导体合金材料中的应变损失最小化。

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