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11. 发明授权

US07081781B2 Charge pump for a low-voltage wide-tuning range phase-locked loop 有权
标题翻译：用于低压宽调谐范围锁相环的电荷泵
公开(公告)号：US07081781B2
公开(公告)日：2006-07-25
申请号：US10817215
申请日：2004-04-02
申请人： Xiang Zhu , Ming Qu , Yongmin Ge
发明人： Xiang Zhu , Ming Qu , Yongmin Ge
IPC分类号： H03L7/06
CPC分类号： H03L7/0896 , H03L7/18
摘要： A charge pump for a differential phase-locked loop (PLL) is provided. The charge pump includes a current switch configured to voltage to source and sink a current in a complementary fashion from a pair of differential output nodes. The charge pump includes a common-mode feedback loop to maintain the charging and discharging of the differential output nodes with respect to a common-mode voltage. Transconductance amplifiers are provided within the common-mode feedback loop to provide greater dynamic range to the charging and discharging of the differential output nodes.
摘要翻译：提供了一种用于差分锁相环（PLL）的电荷泵。电荷泵包括电流开关，其配置为以一对差分输出节点的互补方式对电流进行电压和吸收电流。电荷泵包括共模反馈回路，以保持差分输出节点相对于共模电压的充电和放电。在共模反馈回路内提供跨导放大器，为差分输出节点的充电和放电提供更大的动态范围。

12. 发明授权

US06825733B1 Low jitter integrated phase locked loop with broad tuning range 有权
标题翻译：具有宽调谐范围的低抖动集成锁相环
公开(公告)号：US06825733B1
公开(公告)日：2004-11-30
申请号：US10300190
申请日：2002-11-20
申请人： Ming Qu , Ji Zhao
发明人： Ming Qu , Ji Zhao
IPC分类号： H03B2100
CPC分类号： H03L7/18 , H03L7/095 , H03L7/0995 , H03L7/107 , Y10S331/02
摘要： System and method for providing a low noise signal having a broad tuning range (1 GHz to 10 GHz, or larger), with associated jitter no more than about 10 percent of the selected period of a target output signal. In a first stage, a ring-based VCO phase locked loop system provides a broad tuning range with some associated noise, and a second stage in a first state is relatively transparent, with no substantial differential attenuation based on frequency. After phase lock is achieved, the second stage is switched to a second state with low associated noise and high differential attenuation based on input signal frequency.
摘要翻译：用于提供具有宽调谐范围（1GHz至10GHz或更大）的低噪声信号的系统和方法，相关抖动不超过目标输出信号的选定周期的约10％。在第一级中，基于环的VCO锁相环系统提供具有一些相关噪声的宽调谐范围，并且第一状态中的第二级相对是透明的，基于频率没有实质的差分衰减。在实现相位锁定之后，基于输入信号频率，第二级被切换到具有低相关噪声和高差分衰减的第二状态。

13. 发明授权

US09106770B2 Column drivers with embedded high-speed video interface timing controller 有权
标题翻译：列驱动器具有嵌入式高速视频接口时序控制器
公开(公告)号：US09106770B2
公开(公告)日：2015-08-11
申请号：US13165749
申请日：2011-06-21
申请人： Xin Jin , Zhengyu Yuan , Ming Qu
发明人： Xin Jin , Zhengyu Yuan , Ming Qu
IPC分类号： G09G5/00 , H04N5/00 , G09G3/20
CPC分类号： H04N5/00 , G09G3/20 , G09G5/006 , G09G2310/0221 , G09G2310/027 , G09G2310/0281 , G09G2330/02 , G09G2330/028 , G09G2370/04 , G09G2370/08 , G09G2370/10
摘要： A system and method are disclosed for embedding a timing controller on column drivers which, among other advantages, reduces power consumption and size constraints. A standalone timing controller is eliminated by splitting a video input signal and delivering the signal to each of the column drivers. Timing controller functionality is embedded in each of the column drivers to allow the column drivers to process the received video signal. An auxiliary input used for communication between column drivers and an external system is received by a master column driver. The master column driver communicates with slave column drivers to enable point to point communication between each column driver and the external system.
摘要翻译：公开了一种用于将时序控制器嵌入列驱动器的系统和方法，其特征在于降低功耗和尺寸限制。通过分割视频输入信号并将信号传递给每个列驱动器来消除独立定时控制器。定时控制器功能嵌入在每个列驱动器中，以允许列驱动器处理接收到的视频信号。用于列驱动器和外部系统之间通信的辅助输入由主列驱动器接收。主列驱动程序与从列驱动程序通信，以实现每个列驱动程序和外部系统之间的点对点通信。

14. 发明授权

US09100555B2 Hybrid mode repeater/re-driver for high speed digital video signaling 有权
标题翻译：用于高速数字视频信号的混合模式中继器/重新驱动器
公开(公告)号：US09100555B2
公开(公告)日：2015-08-04
申请号：US13153245
申请日：2011-06-03
申请人： Hongquan Wang , Hongrong Zhang , Zhengyu Yuan , Ming Qu
发明人： Hongquan Wang , Hongrong Zhang , Zhengyu Yuan , Ming Qu
IPC分类号： H04N5/21 , G09G5/00
CPC分类号： H04N5/21 , G09G5/008 , G09G2330/022 , G09G2370/12
摘要： A system and a method are disclosed for a hybrid mode re-driver which, among other advantages, reduces power consumption while maintaining signal integrity. Equalization is performed on a signal to remove distortions such as inter-symbol interference. The signal is then analyzed and the quality of the signal is assessed. In some cases, retiming is then performed on the signal to remove additional signal distortions. In other cases, retiming is not performed and is transmitted to a driver while bypassing retiming components. When retiming components are bypassed, the retiming components are placed in a state of reduced power consumption to reduce system power consumption.
摘要翻译：公开了一种用于混合模式重新驱动器的系统和方法，除了其他优点之外，还能够在维持信号完整性的同时降低功耗。对信号执行均衡，以消除诸如符号间干扰的失真。然后分析信号并评估信号的质量。在某些情况下，对信号进行重新定时以消除额外的信号失真。在其他情况下，不执行重新定时，并在绕过重新定时组件的同时将其发送到驱动程序。当重新定时组件被旁路时，重新定时组件被置于降低功耗的状态以降低系统功耗。

15. 发明授权

US09053673B2 Scalable intra-panel interface 有权
标题翻译：可扩展的面板内接口
公开(公告)号：US09053673B2
公开(公告)日：2015-06-09
申请号：US13070416
申请日：2011-03-23
申请人： Zhengyu Yuan , Jian Jin , Ming Qu , Ding Lu , Zhanpeng Zhang , Qing Ouyang
发明人： Zhengyu Yuan , Jian Jin , Ming Qu , Ding Lu , Zhanpeng Zhang , Qing Ouyang
IPC分类号： G06F3/038 , G09G3/36 , G09G3/20
CPC分类号： G09G3/3611 , G09G3/20 , G09G2300/0426 , G09G2310/027 , G09G2330/06 , G09G2330/12 , G09G2352/00 , G09G2370/08 , G09G2370/14
摘要： A system and a method are disclosed for an intra-panel communication interface which, among other advantages, enhances system reliability and reduces bus width. A timing controller initializes communication with a plurality of source drivers by transmitting link data through a plurality of data channels and monitors source driver status through an auxiliary status channel. The plurality of source drivers share the auxiliary status channel to indicate their status. The timing controller transmits display data to a source driver through a data channel. The display data includes a request for status data from the source driver. The source driver transmits the requested status data to the timing controller via the auxiliary status channel.
摘要翻译：公开了用于面板内通信接口的系统和方法，其特征在于提高了系统可靠性并减少了总线宽度。定时控制器通过多个数据信道发送链路数据并通过辅助状态信道监视源驱动器状态来初始化与多个源驱动器的通信。多个源驱动器共享辅助状态通道以指示其状态。定时控制器通过数据通道将显示数据发送到源驱动器。显示数据包括来自源驱动器的状态数据请求。源驱动器通过辅助状态通道将所请求的状态数据发送到定时控制器。

16. 发明申请

US20120307154A1 HYBRID MODE REPEATER/RE-DRIVER FOR HIGH SPEED DIGITAL VIDEO SIGNALING 有权
标题翻译：用于高速数字视频信号的混合模式重发/再驱动器
公开(公告)号：US20120307154A1
公开(公告)日：2012-12-06
申请号：US13153245
申请日：2011-06-03
申请人： Hongquan Wang , Hongrong Zhang , Zhengyu Yuan , Ming Qu
发明人： Hongquan Wang , Hongrong Zhang , Zhengyu Yuan , Ming Qu
IPC分类号： H04N5/14
CPC分类号： H04N5/21 , G09G5/008 , G09G2330/022 , G09G2370/12
摘要： A system and a method are disclosed for a hybrid mode re-driver which, among other advantages, reduces power consumption while maintaining signal integrity. Equalization is performed on a signal to remove distortions such as inter-symbol interference. The signal is then analyzed and the quality of the signal is assessed. In some cases, retiming is then performed on the signal to remove additional signal distortions. In other cases, retiming is not performed and is transmitted to a driver while bypassing retiming components. When retiming components are bypassed, the retiming components are placed in a state of reduced power consumption to reduce system power consumption.
摘要翻译：公开了一种用于混合模式重新驱动器的系统和方法，除了其他优点之外，还能够在维持信号完整性的同时降低功耗。对信号执行均衡，以消除诸如符号间干扰的失真。然后分析信号并评估信号的质量。在某些情况下，对信号进行重新定时以消除额外的信号失真。在其他情况下，不执行重新定时，并在绕过重新定时组件的同时将其发送到驱动程序。当重新定时组件被旁路时，重新定时组件被置于降低功耗的状态以降低系统功耗。

17. 发明授权

US07397283B2 Digital A/V transmission PHY signaling format conversion, multiplexing, and de-multiplexing 有权
标题翻译：数字A / V传输PHY信令格式转换，复用和解复用
公开(公告)号：US07397283B2
公开(公告)日：2008-07-08
申请号：US11537377
申请日：2006-09-29
申请人： Jimmy Chiu , Ming Qu , Ji Zhao
发明人： Jimmy Chiu , Ming Qu , Ji Zhao
IPC分类号： H03K19/094 , H04N7/01
CPC分类号： H04N5/4403 , H04N5/46 , H04N21/43632
摘要： A circuit includes a configurable receiver circuit, a multiplexer or demultiplexer coupled to the configurable receiver circuit, and a configurable driver circuit coupled to the multiplexer or demultiplexer. The configurable receiver circuit generates an internal format signal which is received by the multiplexer or demultiplexer. The configurable driver circuit receives the internal format signal from the multiplexer or demultiplexer.
摘要翻译：电路包括可配置接收器电路，耦合到可配置接收器电路的多路复用器或解复用器以及耦合到多路复用器或解复用器的可配置驱动器电路。可配置的接收器电路产生由多路复用器或解复用器接收的内部格式信号。可配置驱动器电路从多路复用器或解复用器接收内部格式信号。

18. 发明申请

US20080079462A1 Digital A/V Transmission PHY Signaling Format Conversion, Multiplexing, and De-Multiplexing 有权
标题翻译：数字A / V传输PHY信令格式转换，复用和解复用
公开(公告)号：US20080079462A1
公开(公告)日：2008-04-03
申请号：US11537377
申请日：2006-09-29
申请人： Jimmy Chiu , Ming Qu , Ji Zhao
发明人： Jimmy Chiu , Ming Qu , Ji Zhao
IPC分类号： H03K19/094
CPC分类号： H04N5/4403 , H04N5/46 , H04N21/43632
摘要： A circuit includes a configurable receiver circuit, a multiplexer or demultiplexer coupled to the configurable receiver circuit, and a configurable driver circuit coupled to the multiplexer or demultiplexer. The configurable receiver circuit generates an internal format signal which is received by the multiplexer or demultiplexer. The configurable driver circuit receives the internal format signal from the multiplexer or demultiplexer.
摘要翻译：电路包括可配置接收器电路，耦合到可配置接收器电路的多路复用器或解复用器以及耦合到多路复用器或解复用器的可配置驱动器电路。可配置的接收器电路产生由多路复用器或解复用器接收的内部格式信号。可配置驱动器电路从多路复用器或解复用器接收内部格式信号。

19. 发明授权

US06492877B1 Coupling for LC-based VCO 有权
标题翻译：用于基于LC的VCO的耦合
公开(公告)号：US06492877B1
公开(公告)日：2002-12-10
申请号：US09927289
申请日：2001-08-09
申请人： Edwin Chan , Ming Qu , Ji Zhao
发明人： Edwin Chan , Ming Qu , Ji Zhao
IPC分类号： H03B518
CPC分类号： H03B27/00 , H03B5/1206 , H03B2200/0078
摘要： A two-stage coupling loop system that provides in-phase and quadrature signals in two stages. Each stage includes a signal coupler, an LC-based voltage controlled oscillator (VCO) and in-loop signal buffer that provides an additional controllable phase shift. Inclusion of the buffers in the loop decreases the capacitance load of each VCO.
摘要翻译：两级耦合回路系统，分两阶段提供同相和正交信号。每个级包括信号耦合器，基于LC的压控振荡器（VCO）和环路信号缓冲器，其提供附加的可控相移。将缓冲器包含在环路中会降低每个VCO的电容负载。

20. 发明授权

US08982932B2 Active auxiliary channel buffering 有权
标题翻译：主动辅助通道缓冲
公开(公告)号：US08982932B2
公开(公告)日：2015-03-17
申请号：US12645240
申请日：2009-12-22
申请人： Ming Qu , Zhengyu Yuan , Kochung Lee
发明人： Ming Qu , Zhengyu Yuan , Kochung Lee
IPC分类号： H04B1/38 , H04L5/16 , G09G5/00 , H04L29/06 , H04L29/08
CPC分类号： G09G5/006 , G09G2330/021 , G09G2350/00 , G09G2370/045 , G09G2370/10 , H04L65/4023 , H04L65/4092 , H04L67/34
摘要： A system and a method for communicating configuration data between a source device and a sink are described. An active buffer receives data from an auxiliary communication channel which communicates data between the source device and the sink device. The active buffer modifies data received from the auxiliary communication channel. For example, the active buffer amplifies the received data or electrically reshapes the received data. The modified data is then transmitted from the active buffer to a destination device. In one embodiment, the auxiliary communication channel is bi-directional and upon receiving data from a first device, the active buffer is modified to permit uni-directional transmission of data from the first device to a second device.
摘要翻译：描述用于在源设备和宿之间传送配置数据的系统和方法。主动缓冲器从辅助通信信道接收数据，该辅助通信信道在源设备和宿设备之间传送数据。主动缓冲器修改从辅助通信信道接收到的数据。例如，有源缓冲器放大所接收的数据或电接收数据。然后将修改的数据从活动缓冲器发送到目的地设备。在一个实施例中，辅助通信信道是双向的，并且在从第一设备接收数据时，主动缓冲器被修改以允许将数据从第一设备单向传输到第二设备。

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