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11. 发明授权

US06495853B1 Self-aligned gate semiconductor 有权
标题翻译：自对准栅极半导体
公开(公告)号：US06495853B1
公开(公告)日：2002-12-17
申请号：US09636333
申请日：2000-08-10
申请人： Allison Holbrook , Jiahua Huang , Sunny Cherian
发明人： Allison Holbrook , Jiahua Huang , Sunny Cherian
IPC分类号： H01L2906
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： A method of manufacturing a semiconductor device is provided in which a tunnel dielectric layer and a gate layer are formed on a semiconductor wafer and a trench forming technique is used to define a floating gate structure. An insulator is deposited in the trench whereby the gate layer and the tunnel dielectric layer form a gate which is self-aligned to a tunnel dielectric.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体晶片上形成隧道电介质层和栅极层，并且使用沟槽形成技术来限定浮动栅极结构。绝缘体沉积在沟槽中，由此栅极层和隧道介电层形成与隧道电介质自对准的栅极。

12. 发明授权

US07675104B2 Integrated circuit memory system employing silicon rich layers 有权
标题翻译：集成电路存储系统采用富硅层
公开(公告)号：US07675104B2
公开(公告)日：2010-03-09
申请号：US11461131
申请日：2006-07-31
申请人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
发明人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L21/3081 , H01L21/76224 , H01L27/115 , H01L29/66833
摘要： An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.
摘要翻译：一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

13. 发明授权

US07498222B1 Enhanced etching of a high dielectric constant layer 有权
标题翻译：增强蚀刻高介电常数层
公开(公告)号：US07498222B1
公开(公告)日：2009-03-03
申请号：US11371024
申请日：2006-03-09
申请人： John C. Foster , Scott Bell , Allison Holbrook , Simon S. Chan , Phillip Jones
发明人： John C. Foster , Scott Bell , Allison Holbrook , Simon S. Chan , Phillip Jones
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L29/513 , H01L29/66833
摘要： A high K layer, such as aluminum oxide or hafnium oxide, may be formed with a deposition process that uses an ion implantation to damage portions of the high K material that are to be later etched. More particularly, in one implementation, a semiconductor device is manufactured by forming a first dielectric over a substrate, forming a charge storage element over the first dielectric, forming a second dielectric above the charge storage element, implantation ions into select portions of the second dielectric, and etching the ion implanted select portions of the second dielectric.
摘要翻译：可以用沉积工艺形成高K层，例如氧化铝或氧化铪，所述沉积工艺使用离子注入来破坏将被蚀刻的高K材料的部分。更具体地，在一个实施方式中，通过在衬底上形成第一电介质来形成半导体器件，在第一电介质上形成电荷存储元件，在电荷存储元件上形成第二电介质，将离子注入第二电介质的选择部分并蚀刻第二电介质的离子注入选择部分。

14. 发明申请

US20080171416A1 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀
公开(公告)号：US20080171416A1
公开(公告)日：2008-07-17
申请号：US11653649
申请日：2007-01-12
申请人： Shenging Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
发明人： Shenging Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于结垢。在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。然后在核心单元之间部分蚀刻捕获层。进行捕获层上的氧化物的偏移。并形成顶部氧化物。顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

15. 发明授权

US06472326B1 Reliable particle removal following a process chamber wet clean 失效
标题翻译：处理室湿清洁后可靠的颗粒去除
公开(公告)号：US06472326B1
公开(公告)日：2002-10-29
申请号：US09678421
申请日：2000-10-02
申请人： Allison Holbrook , Greg A. Johnson , Darlene Smith , Omar Serna , Theodros W. Mariam
发明人： Allison Holbrook , Greg A. Johnson , Darlene Smith , Omar Serna , Theodros W. Mariam
IPC分类号： H01L21302
CPC分类号： H01L21/67028 , B08B5/02 , B08B9/08 , C23C16/4407 , Y10S438/905
摘要： Aspects for more reliable particle removal from a semiconductor processing chamber following a chamber wet clean are described. With the present invention, an improved particle removal following wet cleans of semiconductor processing chambers occurs. The present invention creates a turbulent gas flow in a chamber in order to more thoroughly remove particles from the chamber, including those that the wet clean procedures cannot reach. In a straightforward and efficient manner, the turbulent gas flow is created by providing gas in both an upper and lower portion of the chamber substantially simultaneously, including the advantageous use of the backside helium available to chamber processing.
摘要翻译：描述了在腔室湿清洁之后从半导体处理室更可靠的颗粒去除的方面。利用本发明，发生半导体处理室的湿清洗后的改进的颗粒去除。本发明在腔室中产生湍流气流，以便更彻底地从腔室去除颗粒，包括湿法清洁程序无法达到的那些。以直接和有效的方式，通过基本上同时在腔室的上部和下部提供气体来产生湍流气流，包括有利于使用可用于腔室处理的背面氦气。

16. 发明授权

US06358362B1 Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process 有权
标题翻译：用于确定原位局部互连蚀刻工艺的端点的方法和装置
公开(公告)号：US06358362B1
公开(公告)日：2002-03-19
申请号：US09515321
申请日：2000-02-29
申请人： William G. En , Allison Holbrook , Fei Wang
发明人： William G. En , Allison Holbrook , Fei Wang
IPC分类号： G01I346
CPC分类号： B24B37/013 , H01J37/32935 , H01J37/32963 , H01L21/67253 , H01L22/26
摘要： An arrangement is provided for collecting, measuring and analyzing at least two specific wavelengths of optical emissions produced while etching a semiconductor wafer in a plasma chamber to determine an optimal endpoint for the etching process. The arrangement includes a sensor for gathering optical emissions, an interface for converting the intensity of optical emissions into corresponding electrical signals, and a controller for determining an optimal endpoint based on the corresponding electrical signals for the two specific wavelengths and other predetermined threshold data.
摘要翻译：提供了一种用于收集，测量和分析在蚀刻等离子体室中的半导体晶片时产生的至少两个特定波长的光发射以确定用于蚀刻工艺的最佳端点的装置。该装置包括用于收集光发射的传感器，用于将光发射强度转换成相应电信号的接口，以及用于基于两个特定波长和其它预定阈值数据的对应电信号确定最佳端点的控制器。

17. 发明授权

US07906395B2 Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications 有权
标题翻译：通过使用非保形膜的自对准图案化方法，并对闪存和其他半导体应用进行回蚀
公开(公告)号：US07906395B2
公开(公告)日：2011-03-15
申请号：US12891481
申请日：2010-09-27
申请人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
发明人： Shenqing Fang , Kuo-Tung Chang , Tim Thurgate , YouSeok Suh , Allison Holbrook
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.
摘要翻译：公开了一种用于制造具有自对准陷阱层的存储器件的方法，其被优化用于缩放。在本发明中，在电荷捕获层上沉积非保形氧化物，以在芯源极/漏极区域的顶部上形成厚的氧化物，并在STI沟槽的顶部形成空隙。对STI氧化物上的捕获层上的夹断氧化物和薄氧化物进行蚀刻。然后在核心单元之间部分地蚀刻捕获层。进行捕获层上的氧化物的偏移。并形成顶部氧化物。顶部氧化物将剩余的陷阱层转化为氧化物，从而隔离陷阱层。

18. 发明申请

US20080096357A1 METHOD FOR MANUFACTURING A MEMORY DEVICE 审中-公开
标题翻译：用于制造存储器件的方法
公开(公告)号：US20080096357A1
公开(公告)日：2008-04-24
申请号：US11551535
申请日：2006-10-20
申请人： Youseok Suh , Hidehiko Shiraiwa , Allison Holbrook , Angela Hui , Kuo-Tung Chang
发明人： Youseok Suh , Hidehiko Shiraiwa , Allison Holbrook , Angela Hui , Kuo-Tung Chang
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A method for manufacturing a memory device that includes using a gap-filling material that inhibits charge coupling between memory devices. A semiconductor material is provided that has an active region and an isolation region. A charge trapping structure is formed over the active region and a layer of semiconductor material is formed over the charge trapping structure and the isolation region. A masking structure having sidewalls is formed on the layer of semiconductor material. Spacers are formed adjacent the sidewalls and the layer of semiconductor material is etched to form one or more conductive strips having opposing sides. The one or more conductive strips are formed over the active region. A dielectric material is formed adjacent to the opposing sides of each conductive strip. The dielectric material serves as a gap-filling material. A layer of semiconductor material is formed over the one or more conductive strips.
摘要翻译：一种用于制造存储器件的方法，其包括使用禁止存储器件之间的电荷耦合的间隙填充材料。提供了具有有源区和隔离区的半导体材料。在有源区上形成电荷俘获结构，在电荷俘获结构和隔离区上形成一层半导体材料。在半导体材料层上形成具有侧壁的掩模结构。间隔件邻近侧壁形成，并且半导体材料层被蚀刻以形成具有相对侧面的一个或多个导电条。一个或多个导电条形成在有源区上。在每个导电带的相对侧附近形成电介质材料。介电材料用作间隙填充材料。在一个或多个导电条上形成半导体材料层。

19. 发明授权

US06821713B1 Method for lateral trimming of spacers 失效
标题翻译：间隔件横向修剪方法
公开(公告)号：US06821713B1
公开(公告)日：2004-11-23
申请号：US10085242
申请日：2002-02-27
申请人： Allison Holbrook , Jiahua Huang , Sunny Cherian
发明人： Allison Holbrook , Jiahua Huang , Sunny Cherian
IPC分类号： G03F726
CPC分类号： H01L29/6653 , H01L21/31116 , H01L21/32137 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： Spacer etch trim techniques are provided. The method controllably trims a multi-film stack spacer utilizing a self-limiting etch technique. The method may use a dry etch etcher with low bias power. The dry etch process may also use other modified parameters, such as gas flows and various pressures.
摘要翻译：提供间隔蚀刻修剪技术。该方法利用自限制蚀刻技术可控制地修整多层叠层间隔物。该方法可以使用具有低偏压功率的干蚀刻蚀刻机。干法蚀刻工艺也可以使用其它改进的参数，例如气流和各种压力。

20. 发明授权

US06605843B1 Fully depleted SOI device with tungsten damascene contacts and method of forming same 失效
标题翻译：具有钨镶嵌触点的完全耗尽的SOI器件及其形成方法
公开(公告)号：US06605843B1
公开(公告)日：2003-08-12
申请号：US09637450
申请日：2000-08-11
申请人： Zoran Krivokapic , Allison Holbrook , Sunny Cherian , Kai Yang
发明人： Zoran Krivokapic , Allison Holbrook , Sunny Cherian , Kai Yang
IPC分类号： H01L2701
CPC分类号： H01L29/66772 , H01L21/84 , H01L29/78612 , H01L29/78618 , H01L29/78621
摘要： A fully depleted field effect transistor formed in a silicon on insulator (SOI) substrate includes a body region formed in a silicon device layer over an isolation layer of the SOI substrate. A gate is positioned above the body region and includes a base gate region adjacent the body region and a wide top gate region formed of tungsten damascene and spaced apart from the body region. An inverted T-shaped central channel region is formed between adjacent source regions and drain region in the body region.
摘要翻译：形成在绝缘体上硅（SOI））衬底上的完全耗尽的场效应晶体管包括形成在SOI衬底的隔离层上的硅器件层中的体区。栅极位于身体区域上方，并且包括邻近身体区域的基极栅极区域和由钨镶嵌形成并与身体区域间隔开的宽的顶部栅极区域。在身体区域中的相邻的源极区域和漏极区域之间形成倒置的T形中心沟道区域。

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