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11. 发明授权

US06962857B1 Shallow trench isolation process using oxide deposition and anneal 有权
标题翻译：使用氧化物沉积和退火的浅沟槽隔离工艺
公开(公告)号：US06962857B1
公开(公告)日：2005-11-08
申请号：US10358966
申请日：2003-02-05
申请人： Minh-Van Ngo , Ming-Ren Lin , Eric N. Paton , Haihong Wang , Qi Xiang , Jung-Suk Goo
发明人： Minh-Van Ngo , Ming-Ren Lin , Eric N. Paton , Haihong Wang , Qi Xiang , Jung-Suk Goo
IPC分类号： H01L21/76 , H01L21/762 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/76224 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in a strained silicon (SMOS) process. The liner for the trench is formed from a layer deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be an LPCVD. An annealing step can be utilized to form the liner.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。用于沟槽的衬垫由沉积在低温过程中的层形成，其减少锗除气。低温过程可以是LPCVD。可以使用退火步骤来形成衬垫。

12. 发明授权

US06730576B1 Method of forming a thick strained silicon layer and semiconductor structures incorporating a thick strained silicon layer 有权
标题翻译：形成厚应变硅层的方法和掺入厚应变硅层的半导体结构
公开(公告)号：US06730576B1
公开(公告)日：2004-05-04
申请号：US10335447
申请日：2002-12-31
申请人： Haihong Wang , Paul R. Besser , Jung-Suk Goo , Minh V. Ngo , Eric N. Paton , Qi Xiang
发明人： Haihong Wang , Paul R. Besser , Jung-Suk Goo , Minh V. Ngo , Eric N. Paton , Qi Xiang
IPC分类号： H01L21762
CPC分类号： H01L29/7833 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/76224 , H01L29/1054 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： A strained silicon layer is grown on a layer of silicon germanium and a layer of silicon germanium is grown on the strained silicon in a single continuous in situ deposition process with the strained silicon. Shallow trench isolations are formed in the lower layer of silicon germanium prior to formation of the strained silicon layer. The two silicon germanium layers effectively provide dual substrates at both surfaces of the strained silicon layer that serve to maintain the tensile strain of the strained silicon layer and resist the formation of misfit dislocations that might otherwise result from temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown without significant misfit dislocations during later processing is effectively doubled for a given germanium content of the silicon germanium layers. The formation of shallow trench isolations prior to formation of the strained silicon layer avoids subjecting the strained silicon layer to extreme thermal stresses and further reduces the formation of misfit dislocations.
摘要翻译：应变硅层在硅锗层上生长，并且在应变硅上生长硅锗层，并在应变硅中进行单次连续原位沉积工艺。在形成应变硅层之前，在硅锗的下层形成浅沟槽隔离。两个硅锗层有效地在应变硅层的两个表面上提供双重衬底，其用于维持应变硅层的拉伸应变，并抵抗由加工过程中的温度变化引起的失配位错的形成。因此，对于硅锗层的给定锗含量，可以在后续处理期间可以生长而不显着失配位错的应变硅的临界厚度被有效地加倍。在形成应变硅层之前形成浅沟槽隔离避免使应变硅层受到极端的热应力，并进一步减少失配位错的形成。

13. 发明授权

US07462549B2 Shallow trench isolation process and structure with minimized strained silicon consumption 有权
标题翻译：浅沟槽隔离工艺和结构，使应变硅消耗最小化
公开(公告)号：US07462549B2
公开(公告)日：2008-12-09
申请号：US10755602
申请日：2004-01-12
申请人： Qi Xiang , James N. Pan , Jung-Suk Goo
发明人： Qi Xiang , James N. Pan , Jung-Suk Goo
IPC分类号： H01L21/76
CPC分类号： H01L29/66742 , H01L21/76283 , H01L29/458 , H01L29/7842 , H01L29/78687 , Y10S438/933
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。在形成沟槽之后形成应变材料。该方法可以用在盒层上方的化合物半导体层上。

14. 发明授权

US07170084B1 Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication 有权
标题翻译：具有改善的源极/漏极延伸掺杂剂扩散电阻的应变硅MOSFET及其制造方法
公开(公告)号：US07170084B1
公开(公告)日：2007-01-30
申请号：US10872707
申请日：2004-06-21
申请人： Qi Xiang , Jung-Suk Goo , Haihong Wang
发明人： Qi Xiang , Jung-Suk Goo , Haihong Wang
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66477 , H01L21/26586 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.
摘要翻译：在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

15. 发明授权

US06955969B2 Method of growing as a channel region to reduce source/drain junction capacitance 有权
标题翻译：生长为沟道区域以减少源极/漏极结电容的方法
公开(公告)号：US06955969B2
公开(公告)日：2005-10-18
申请号：US10654497
申请日：2003-09-03
申请人： Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
发明人： Ihsan J. Djomehri , Jung-Suk Goo , Srinath Krishnan , Witold P. Maszara , James N. Pan , Qi Xiang
IPC分类号： H01L21/20 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/78 , H01L21/336 , H01L21/338
CPC分类号： H01L29/0847 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L29/0653 , H01L29/1054 , H01L29/78
摘要： A method of forming a channel region for a transistor includes forming a layer of silicon germanium (SiGe) above a substrate, forming an oxide layer above the SiGe layer wherein the oxide layer includes an aperture in a channel area and the aperture is filled with a SiGe feature, depositing a layer having a first thickness above the oxide layer and the SiGe feature, and forming source and drain regions in the layer.
摘要翻译：形成用于晶体管的沟道区的方法包括在衬底上形成硅锗层（SiGe），在SiGe层上形成氧化物层，其中氧化物层包括沟道区中的孔，并且孔填充有 SiGe特征，在氧化物层上沉积具有第一厚度的层和SiGe特征，以及在该层中形成源区和漏区。

16. 发明授权

US06902991B2 Semiconductor device having a thick strained silicon layer and method of its formation 有权
标题翻译：具有厚的应变硅层的半导体器件及其形成方法
公开(公告)号：US06902991B2
公开(公告)日：2005-06-07
申请号：US10282513
申请日：2002-10-24
申请人： Qi Xiang , Jung-Suk Goo , Haihong Wang
发明人： Qi Xiang , Jung-Suk Goo , Haihong Wang
IPC分类号： H01L21/20 , H01L21/205 , H01L21/336 , H01L21/337 , H01L29/10 , H01L21/04
CPC分类号： H01L29/1054 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/66795 , H01L29/66893
摘要： A strained silicon layer is grown on a layer of silicon germanium and a second layer of silicon germanium is grown on the layer of strained silicon in a single continuous in situ deposition process. Both layers of silicon germanium may be grown in situ with the strained silicon. This construction effectively provides dual substrates at both sides of the strained silicon layer to support the tensile strain of the strained silicon layer and to resist the formation of misfit dislocations that may be induced by temperature changes during processing. Consequently the critical thickness of strained silicon that can be grown on substrates having a given germanium content is effectively doubled. The silicon germanium layer overlying the strained silicon layer may be maintained during MOSFET processing to resist creation of misfit dislocations in the strained silicon layer up to the time of formation of gate insulating material.
摘要翻译：在硅锗层上生长应变硅层，并且在单个连续原位沉积工艺中，在应变硅层上生长第二层硅锗。硅锗的两层可以用应变硅原位生长。这种结构在应变硅层的两侧有效地提供了两个基板，以支撑应变硅层的拉伸应变，并且抵抗可能在加工过程中温度变化引起的失配位错的形成。因此，可以在具有给定锗含量的衬底上生长的应变硅的临界厚度被有效地加倍。覆盖应变硅层的硅锗层可以在MOSFET加工过程中保持，以抵抗在形成栅极绝缘材料时产生应变硅层中的失配位错。

17. 发明授权

US06900143B1 Strained silicon MOSFETs having improved thermal dissipation 有权
标题翻译：应变硅MOSFET具有改善的散热
公开(公告)号：US06900143B1
公开(公告)日：2005-05-31
申请号：US10658963
申请日：2003-09-09
申请人： James N. Pan , Jung-Suk Goo , Qi Xiang
发明人： James N. Pan , Jung-Suk Goo , Qi Xiang
IPC分类号： H01L21/285 , H01L21/336 , H01L21/461 , H01L29/10 , H01L29/78
CPC分类号： H01L29/6659 , H01L21/28525 , H01L29/1054 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： The thermal conductivity of strained silicon MOSFETs and strained silicon SOI MOSFETs is improved by providing a silicon germanium carbide thermal dissipation layer beneath a silicon germanium layer on which strained silicon is grown. The silicon germanium carbide thermal dissipation layer has a higher thermal conductivity than silicon germanium, thus providing more efficient removal of thermal energy generated in active regions.
摘要翻译：通过在其上生长应变硅的硅锗层之下提供硅碳化硅散热层来改善应变硅MOSFET和应变硅SOI MOSFET的导热性。硅碳化硅散热层具有比硅锗更高的热导率，从而提供更有效地去除在活性区域中产生的热能。

18. 发明申请

US20050054149A1 METHOD FOR INTEGRATING METALS HAVING DIFFERENT WORK FUNCTIONS TO FOM CMOS GATES HAVING A HIGH-K GATE DIELECTRIC AND RELATED STRUCTURE 有权
标题翻译：具有不同工作功能的金属的方法用于具有高K栅介质和相关结构的FOM CMOS栅
公开(公告)号：US20050054149A1
公开(公告)日：2005-03-10
申请号：US10654689
申请日：2003-09-04
申请人： Qi Xiang , Huicai Zhong , Jung-Suk Goo , Allison Holbrook , Joong Jeon , George Kluth
发明人： Qi Xiang , Huicai Zhong , Jung-Suk Goo , Allison Holbrook , Joong Jeon , George Kluth
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/336
CPC分类号： H01L21/823857 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518
摘要： According to one exemplary embodiment, a method for integrating first and second metal layers on a substrate to form a dual metal NMOS gate and PMOS gate comprises depositing a dielectric layer over an NMOS region and a PMOS region of the substrate. The method further comprises depositing the first metal layer over dielectric layer. The method further comprises depositing the second metal layer over the first metal layer. The method further comprises implanting nitrogen in the NMOS region of substrate and converting a first portion of the first metal layer into a metal oxide layer and converting a second portion of the first metal layer into metal nitride layer. The method further comprises forming the NMOS gate and the PMOS gate, where the NMOS gate comprises a segment of metal nitride layer and the PMOS gate comprises a segment of the metal oxide layer.
摘要翻译：根据一个示例性实施例，一种用于在衬底上将第一和第二金属层集成以形成双金属NMOS栅极和PMOS栅极的方法包括在衬底的NMOS区域和PMOS区域上沉积介电层。该方法还包括在电介质层上沉积第一金属层。该方法还包括在第一金属层上沉积第二金属层。该方法还包括在衬底的NMOS区域中注入氮气，并将第一金属层的第一部分转变为金属氧化物层，并将第一金属层的第二部分转换为金属氮化物层。该方法还包括形成NMOS栅极和PMOS栅极，其中NMOS栅极包括一段金属氮化物层，PMOS栅极包括金属氧化物层的一段。

19. 发明授权

US06756276B1 Strained silicon MOSFET having improved source/drain extension dopant diffusion resistance and method for its fabrication 有权
标题翻译：具有改善的源极/漏极延伸掺杂剂扩散电阻的应变硅MOSFET及其制造方法
公开(公告)号：US06756276B1
公开(公告)日：2004-06-29
申请号：US10335522
申请日：2002-12-31
申请人： Qi Xiang , Jung-Suk Goo , Haihong Wang
发明人： Qi Xiang , Jung-Suk Goo , Haihong Wang
IPC分类号： H01L21336
CPC分类号： H01L29/66477 , H01L21/26586 , H01L29/1045 , H01L29/1054 , H01L29/665
摘要： An n-type MOSFET (NMOS) is implemented on a substrate having an epitaxial layer of strained silicon formed on a layer of silicon germanium. The MOSFET includes first halo regions formed in the strained silicon layer that extent toward the channel region beyond the ends of shallow source and drain extensions. Second halo regions formed in the underlying silicon germanium layer extend toward the channel region beyond the ends of the shallow source and drain extensions and extend deeper into the silicon germanium layer than the shallow source and drain extensions. The p-type dopant of the first and second halo regions slows the high rate of diffusion of the n-type dopant of the shallow source and drain extensions through the silicon germanium toward the channel region. By counteracting the increased diffusion rate of the n-type dopant in this manner, the shallow source and drain extension profiles are maintained and the risk of degradation by short channel effects is reduced.
摘要翻译：在具有形成在硅锗层上的应变硅的外延层的衬底上实施n型MOSFET（NMOS）。 MOSFET包括形成在应变硅层中的第一晕圈，其范围朝向超过浅源极和漏极延伸端的沟道区域。形成在下面的硅锗层中的第二晕圈延伸到超过浅源极和漏极延伸端的沟道区，并且比浅源极和漏极延伸部更深地延伸到硅锗层中。第一和第二晕圈区域的p型掺杂剂减缓了浅源极和漏极延伸部分的n型掺杂剂通过硅锗朝向沟道区的高扩散速率。通过以这种方式抵消增加的n型掺杂剂的扩散速率，维持浅的源极和漏极延伸分布，并且降低由短沟道效应引起的退化的风险。

20. 发明授权

US07732336B2 Shallow trench isolation process and structure with minimized strained silicon consumption 有权
标题翻译：浅沟槽隔离工艺和结构，使应变硅消耗最小化
公开(公告)号：US07732336B2
公开(公告)日：2010-06-08
申请号：US12115473
申请日：2008-05-05
申请人： Qi Xiang , James N. Pan , Jung-Suk Goo
发明人： Qi Xiang , James N. Pan , Jung-Suk Goo
IPC分类号： H01L21/311
CPC分类号： H01L29/66742 , H01L21/76283 , H01L29/458 , H01L29/7842 , H01L29/78687 , Y10S438/933
摘要： A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The strained material is formed after the trench is formed. The process can be utilized on a compound semiconductor layer above a box layer.
摘要翻译：集成电路（IC）的制造方法利用浅沟槽隔离（STI）技术。浅沟槽隔离技术用于应变硅（SMOS）工艺。在形成沟槽之后形成应变材料。该方法可以用在盒层上方的化合物半导体层上。

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