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11. 发明申请

US20070099388A1 Source/Drain Extensions Having Highly Activated and Extremely Abrupt Junctions 有权
标题翻译：源极/漏极延伸器具有高度活化和极度突出的接合点
公开(公告)号：US20070099388A1
公开(公告)日：2007-05-03
申请号：US11614300
申请日：2006-12-21
申请人： Amitabh Jain
发明人： Amitabh Jain
IPC分类号： H01L21/336 , H01L29/94 , H01L29/76 , H01L31/00
CPC分类号： H01L29/66636 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations 90 and depositing SiGe within the recess to form SiGe source/drain extensions 90. Dopants are implanted into the SiGe source/drain extensions 90 and the semiconductor wafer 10 is annealed. Also, a transistor source/drain region 80, 90 having a SiGe source/drain extension 90 that contains evenly distributed dopants, is highly doped, and has highly abrupt edges.
摘要翻译：一种在半导体晶片内制造晶体管的方法。该方法可以包括在源极/漏极扩展位置90处蚀刻凹陷并在凹槽内沉积SiGe以形成SiGe源极/漏极延伸部90。将掺杂剂注入到SiGe源极/漏极延伸部分90中，并且半导体晶片10被退火。此外，具有含有均匀分布的掺杂剂的SiGe源极/漏极延伸部90的晶体管源极/漏极区域80,90是高度掺杂的，并且具有高度突变的边缘。

12. 发明申请

US20060154411A1 CMOS transistors and methods of forming same 审中-公开
标题翻译： CMOS晶体管及其形成方法
公开(公告)号：US20060154411A1
公开(公告)日：2006-07-13
申请号：US11372430
申请日：2006-03-09
申请人： Haowen Bu , Brian Hornung , P.R. Chidambaram , Amitabh Jain , Rajesh Khamankar , Nandu Mahalingam , Srinivansan Chakravarthi
发明人： Haowen Bu , Brian Hornung , P.R. Chidambaram , Amitabh Jain , Rajesh Khamankar , Nandu Mahalingam , Srinivansan Chakravarthi
IPC分类号： H01L21/338 , H01L21/31
CPC分类号： H01L21/26506 , H01L21/265 , H01L21/26513 , H01L21/2658 , H01L21/3185 , H01L21/324 , H01L21/823814 , H01L21/823864 , H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843 , H01L29/7845
摘要： The present invention teaches the formation of CMOS transistors using interfacial nitrogen at the interface between the lightly doped extension regions and an overlying insulating layer in combination with a capping layer of silicon nitride, both prior to the final source/drain anneal. Doses and energies may be increased for the P-channel lightly-doped drain, source and drain regions. The resulting transistors exhibit desirably high drive current and low off-state leakage current and overlap capacitance.
摘要翻译：本发明教导了在最终的源极/漏极退火之前，在轻掺杂的延伸区域之间的界面处的界面氮和与氮化硅覆盖层结合的上覆绝缘层的CMOS晶体管的形成。 P沟道轻掺杂漏极，源极和漏极区域的剂量和能量可能会增加。所得到的晶体管显示期望的高驱动电流和低截止状态的漏电流和重叠电容。

13. 发明申请

US20050133876A1 Reduced hydrogen sidewall spacer oxide 有权
公开(公告)号：US20050133876A1
公开(公告)日：2005-06-23
申请号：US10739973
申请日：2003-12-17
申请人： Haowen Bu , Clinton Montgomery , Amitabh Jain
发明人： Haowen Bu , Clinton Montgomery , Amitabh Jain
IPC分类号： H01L21/314 , H01L21/316 , H01L21/336 , H01L21/338 , H01L29/49 , H01L29/76 , H01L29/78 , H01L31/062
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02362 , H01L21/3145 , H01L21/31612 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

14. 发明申请

US20050133835A1 Reduced hydrogen sidewall spacer oxide 有权
标题翻译：还原氢侧壁间隔氧化物
公开(公告)号：US20050133835A1
公开(公告)日：2005-06-23
申请号：US10959689
申请日：2004-10-06
申请人： Haowen Bu , Clinton Montgomery , Amitabh Jain
发明人： Haowen Bu , Clinton Montgomery , Amitabh Jain
IPC分类号： H01L21/314 , H01L21/316 , H01L21/336 , H01L21/338 , H01L29/49 , H01L29/76 , H01L29/78 , H01L31/062
CPC分类号： H01L29/4983 , H01L21/0214 , H01L21/02164 , H01L21/02271 , H01L21/02274 , H01L21/02362 , H01L21/3145 , H01L21/31612 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.
摘要翻译：本发明的一个实施例是制造半导体结构10的方法，其中通过无氢前体CVD工艺形成间隔氧化物层90。本发明的另一实施例是具有氢含量小于1％的间隔氧化物层90的半导体结构10。

15. 发明授权

US08659112B2 Carbon and nitrogen doping for selected PMOS transistor on an integrated circuit 有权
标题翻译：在集成电路上选择PMOS晶体管的碳氮掺杂
公开(公告)号：US08659112B2
公开(公告)日：2014-02-25
申请号：US12967109
申请日：2010-12-14
申请人： Mahalingam Nandakumar , Amitabh Jain
发明人： Mahalingam Nandakumar , Amitabh Jain
IPC分类号： H01L21/70 , H01L27/088 , H01L21/8234
CPC分类号： H01L21/823412 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L21/28202 , H01L21/823418 , H01L21/823462 , H01L29/1083 , H01L29/66537 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.
摘要翻译：形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。在源极和漏极之间进行源极/漏极退火。

16. 发明申请

US20140011340A1 Method of Forming a CMOS Device with a Stressed-Channel NMOS Transistor and a Strained-Channel PMOS Transistor 有权
标题翻译：用高压沟道NMOS晶体管和应变通道PMOS晶体管形成CMOS器件的方法
公开(公告)号：US20140011340A1
公开(公告)日：2014-01-09
申请号：US13541957
申请日：2012-07-05
申请人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
发明人： Seung-Chul Song , Amitabh Jain , Deborah J. Riley
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823857 , H01L27/092 , H01L29/6653 , H01L29/6656 , H01L29/66636 , H01L29/7833 , H01L29/7834 , H01L29/7847 , H01L29/7848
摘要： A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.
摘要翻译：形成应力通道NMOS晶体管和应变通道PMOS晶体管的方法在植入n型源极和漏极掺杂剂之前形成p型源极和漏极区，并且形成应力记忆层，由此减小施加到n - 沟道的PMOS晶体管。此外，在形成p型源极和漏极区之后，但在植入n型掺杂剂之前，形成非导电层。不导电层允许实现较浅的n型植入物，并且还用作应力记忆层的缓冲层。

17. 发明授权

US08372750B2 Method and system for improved nickel silicide 有权
标题翻译：改善硅化镍的方法和系统
公开(公告)号：US08372750B2
公开(公告)日：2013-02-12
申请号：US12890100
申请日：2010-09-24
申请人： Amitabh Jain , Peijun Chen , Jorge A. Kittl
发明人： Amitabh Jain , Peijun Chen , Jorge A. Kittl
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L21/823807 , H01L21/823835 , H01L29/665 , H01L29/78
摘要： According to one embodiment of the invention, a method for nickel silicidation includes providing a substrate having a source region, a gate region, and a drain region, forming a source in the source region and a drain in the drain region, annealing the source and the drain, implanting, after the annealing the source and the drain, a heavy ion in the source region and the drain region, depositing a nickel layer in each of the source and drain regions, and heating the substrate to form a nickel silicide region in each of the source and drain regions by heating the substrate.
摘要翻译：根据本发明的一个实施例，一种用于镍硅化的方法包括提供具有源极区，栅极区和漏极区的衬底，在源区中形成源极和在漏极区中形成漏极，退火源和漏极，在源极和漏极退火之后注入源区域和漏极区域中的重离子，在源极和漏极区域中的每一个中沉积镍层，并加热衬底以形成硅化镍区域每个源极和漏极区域通过加热衬底。

18. 发明授权

US07795122B2 Antimony ion implantation for semiconductor components 有权
标题翻译：半导体元件的锑离子注入
公开(公告)号：US07795122B2
公开(公告)日：2010-09-14
申请号：US11725927
申请日：2007-03-20
申请人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank S. Ekbote
发明人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank S. Ekbote
IPC分类号： H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L29/6653 , H01L29/7833
摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.
摘要翻译：公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻同时还抑制短沟道效应。还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

19. 发明授权

US07615458B2 Activation of CMOS source/drain extensions by ultra-high temperature anneals 有权
标题翻译：通过超高温退火激活CMOS源极/漏极延伸
公开(公告)号：US07615458B2
公开(公告)日：2009-11-10
申请号：US11764980
申请日：2007-06-19
申请人： Amitabh Jain , Manoj Mehrotra
发明人： Amitabh Jain , Manoj Mehrotra
IPC分类号： H01L21/331
CPC分类号： H01L21/2652 , H01L21/2255 , H01L21/268 , H01L21/2686 , H01L21/823814 , H01L29/6659
摘要： A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底上形成栅极电介质层。在栅极电介质层上形成栅电极。将掺杂剂注入到衬底的延伸区域中，其中掺杂剂的量保留在与栅电极相邻的电介质层中。衬底在约1000℃或更高的温度下进行退火，以使掺杂剂的量的至少一部分扩散到半导体衬底中。

20. 发明授权

US07511350B2 Nickel alloy silicide including indium and a method of manufacture therefor 有权
标题翻译：包括铟的镍合金硅化物及其制造方法
公开(公告)号：US07511350B2
公开(公告)日：2009-03-31
申请号：US12018313
申请日：2008-01-23
申请人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
发明人： Peijun J. Chen , Duofeng Yue , Amitabh Jain , Sue Crank , Thomas D. Bonifield , Homi Mogul
IPC分类号： H01L29/78
CPC分类号： H01L21/28518 , H01L21/26513 , H01L21/26586 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
摘要翻译：本发明提供一种半导体器件，一种制造方法以及一种用于制造包括该半导体器件的集成电路的方法。除了其他元件之外，半导体器件可以包括位于衬底上的栅极结构，栅极结构包括栅极电介质层和栅极电极层。该半导体器件还可以包括位于衬底中或栅极结构附近的源极/漏极区域和位于源极/漏极区域中的镍合金硅化物，所述镍合金硅化物具有位于其中的铟的量。

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