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11. 发明申请

US20110074477A1 Techniques for Providing Reduced Duty Cycle Distortion 有权
标题翻译：提供减少占空比失真的技术
公开(公告)号：US20110074477A1
公开(公告)日：2011-03-31
申请号：US12642502
申请日：2009-12-18
申请人： Pradeep Nagarajan , Yan Chong , Chiakang Sung , Joseph Huang
发明人： Pradeep Nagarajan , Yan Chong , Chiakang Sung , Joseph Huang
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/134 , H03K5/1565 , H03K2005/00065
摘要： A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuits comprises variable delay blocks and fixed delay blocks that are coupled to form at least two delay paths for an input signal through the delay circuit to generate a delayed output signal. Delays of the variable delay blocks in the delay circuits vary based on the output signal of the phase detector. Each of the delay circuits reroutes the input signal through a different one of the delay paths to generate the delayed output signal based on the output signal of the phase detector during operation of the feedback loop circuit. Each of the variable delay blocks and the fixed delay blocks is inverting.
摘要翻译：反馈回路包括相位检测器和延迟电路。相位检测器基于延迟周期信号产生输出信号。延迟电路在延迟链中耦合，延迟链延迟了延迟的周期信号。每个延迟电路包括可变延迟块和固定延迟块，其被耦合以形成用于通过延迟电路的输入信号的至少两个延迟路径以产生延迟的输出信号。延迟电路中的可变延迟块的延迟基于相位检测器的输出信号而变化。每个延迟电路通过不同的一个延迟路径重新路由输入信号，以在反馈回路电路的操作期间基于相位检测器的输出信号产生延迟的输出信号。每个可变延迟块和固定延迟块都是反相的。

12. 发明授权

US08593195B1 High performance memory interface circuit architecture 有权
标题翻译：高性能存储器接口电路架构
公开(公告)号：US08593195B1
公开(公告)日：2013-11-26
申请号：US13614526
申请日：2012-09-13
申请人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
发明人： Joseph Huang , Chiakang Sung , Philip Pan , Yan Chong , Andy L. Lee , Brian D. Johnson
IPC分类号： H03H11/16
CPC分类号： H03L7/0812 , G11C7/22 , G11C7/222 , H03L7/0805
摘要： A programmable memory interface circuit includes a programmable DLL delay chain, a phase offset control circuit and a programmable DQS delay chain. The DLL delay chain uses a set of serially connected delay cells, a programmable switch, a phase detector and a digital counter to generate a coarse phase shift control setting. The coarse phase shift control setting is then used to pre-compute a static residual phase shift control setting or generate a dynamic residual phase shift control setting, one of which is chosen by the phase offset control circuit to be added to or subtracted from the coarse phase shift control setting to generate a fine phase shift control setting. The coarse and fine phase shift control settings work in concert to generate a phase-delayed DQS signal that is center-aligned to its associated DQ signals.
摘要翻译：可编程存储器接口电路包括可编程DLL延迟链，相位偏移控制电路和可编程DQS延迟链。 DLL延迟链使用一组串行连接的延迟单元，可编程开关，相位检测器和数字计数器来产生粗略的相移控制设置。然后，粗略的相移控制设置用于预先计算静态残留相移控制设置或生成动态残留相移控制设置，其中一个由相位偏移控制电路选择以被加到或从粗略相移控制设置，以产生精细的相移控制设置。粗调和精细相移控制设置一致地产生相位延迟的DQS信号，其中心对准其相关联的DQ信号。

13. 发明授权

US07710149B1 Input buffer for multiple differential I/O standards 失效
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US07710149B1
公开(公告)日：2010-05-04
申请号：US12190530
申请日：2008-08-12
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiabao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiabao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K19/094 , H03K19/0948
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

14. 发明授权

US07671579B1 Method and apparatus for quantifying and minimizing skew between signals 失效
标题翻译：用于量化和最小化信号之间的偏差的方法和装置
公开(公告)号：US07671579B1
公开(公告)日：2010-03-02
申请号：US11470898
申请日：2006-09-07
申请人： Yan Chong , Joseph Huang , Chiakang Sung , Eric Choong-Yin Chang , Peter Boyle , Adam J. Wright
发明人： Yan Chong , Joseph Huang , Chiakang Sung , Eric Choong-Yin Chang , Peter Boyle , Adam J. Wright
IPC分类号： G01R23/175 , G08B23/00
CPC分类号： H03K5/135 , G01R31/3016 , G01R31/31725 , G01R31/318516 , H03K5/14 , H03K5/1504
摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.
摘要翻译：使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。两个信号之间的偏差被量化为测量延迟的差。在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

15. 发明授权

US07425844B1 Input buffer for multiple differential I/O standards 有权
标题翻译：用于多个差分I / O标准的输入缓冲器
公开(公告)号：US07425844B1
公开(公告)日：2008-09-16
申请号：US11697299
申请日：2007-04-06
申请人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
发明人： Jonathan Chung , In Whan Kim , Philip Pan , Chiakang Sung , Bonnie Wang , Xiaobao Wang , Yan Chong , Gopinath Rangan , Khai Nguyen , Tzung-Chin Chang , Joseph Huang
IPC分类号： H03K19/094 , H03K19/0948 , H03K17/00
CPC分类号： H03K19/018585
摘要： An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.
摘要翻译：输入缓冲器电路具有多个选择性启用的差分放大器电路，其中每个差分放大器被配置为与特定差分I / O标准及其对应的输入工作范围兼容。例如，输入缓冲器可以具有适合于在宽输入工作范围内接收LVDS差分输入信号的两个差分放大器，以及适合于接收PCML差分输入信号的另一差分放大器。一个或多个控制信号例如可编程地提供给输入缓冲器，以选择性地启用给定的I / O标准所需的差分放大器。

16. 发明授权

US07330051B1 Innovated technique to reduce memory interface write mode SSN in FPGA 有权
标题翻译：在FPGA中减少存储器接口写模式SSN的创新技术
公开(公告)号：US07330051B1
公开(公告)日：2008-02-12
申请号：US11354766
申请日：2006-02-14
申请人： Joseph Huang , Chiakang Sung , Michael H. M. Chu , Yan Chong
发明人： Joseph Huang , Chiakang Sung , Michael H. M. Chu , Yan Chong
IPC分类号： H03K19/173
CPC分类号： H03K19/17744
摘要： The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.
摘要翻译：通过可编程器件的操作产生的同时开关噪声的量可以通过减少引脚数目同时减少。 I / O bank可以包括多个I / O引脚子集或DQS组，每组都被编程为在不同的时间切换，使得各个引脚的切换时间可以在每个系统时钟周期内交错。可编程延迟元件可用于控制每个子集的延迟。可编程元件可以放置在系统时钟和输出寄存器之间，以便延迟寄存器对时钟信号的接收，从而延迟输出缓冲器的切换。可编程延迟元件也可以放置在输出寄存器和输出缓冲器之间，以便延迟输出缓冲器的输出数据的接收和随后的切换。

17. 发明授权

US07324405B1 DQS postamble filtering 有权
标题翻译： DQS后同步码过滤
公开(公告)号：US07324405B1
公开(公告)日：2008-01-29
申请号：US11368369
申请日：2006-03-03
申请人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
发明人： Sanjay K. Charagulla , Chiakang Sung , Joseph Huang , Bonnie I. Wang , Yan Chong
IPC分类号： G11C8/00
CPC分类号： H03K5/135 , G11C7/1051 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/22 , H03M9/00
摘要： Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.
摘要翻译：用于在高速数据接口处过滤信号的电路，方法和装置。一个示例性实施例被特别地配置为在由双数据速率存储器接口接收的数据突发结束时对时钟信号进行滤波。时钟输入端口与输入单元连接或断开。当接收到数据脉冲串时，时钟输入端口连接到输入单元。当数据突发结束时，时钟输入端口与输入单元断开连接。在具体实施例中，接收到指示数据脉冲串即将开始并且时钟输入端口连接到输入单元的信号。该信号随后改变指示正在接收最后一个数据位的状态。当接收到与最后一个数据位相对应的最后一个时钟沿时，时钟输入端口与输入单元断开。

18. 发明授权

US07200769B1 Self-compensating delay chain for multiple-date-rate interfaces 有权
标题翻译：多速率接口的自补偿延迟链
公开(公告)号：US07200769B1
公开(公告)日：2007-04-03
申请号：US10037861
申请日：2002-01-02
申请人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
发明人： Yan Chong , Chiakang Sung , Bonnie I. Wang , Joseph Huang , Xiaobao Wang , Philip Pan , Tzung-Chin Chang
IPC分类号： G06F1/04
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/222 , G11C2207/108 , H03L7/0805 , H03L7/0814 , H03L7/091
摘要： Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.
摘要翻译：用于延迟多数据速率接口的时钟信号的方法和装置。一种装置提供一种集成电路，其包括配置成接收第一时钟信号的分频器和被配置为接收来自分频器的输出的第一可变延迟块。还包括相位检测器，被配置为接收第一时钟信号和来自第一可变延迟块的输出，以及配置为接收来自相位检测器的输出的上/下计数器。第二可变延迟块被配置为接收第二时钟信号，并且多个触发器被配置为从第二可变延迟块接收输出。第一可变延迟块和第二可变延迟块被配置为从加/减计数器接收输出。

19. 发明授权

US06992947B1 Dual-port SRAM in a programmable logic device 失效
公开(公告)号：US06992947B1
公开(公告)日：2006-01-31
申请号：US10696209
申请日：2003-10-28
申请人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong
发明人： Philip Y. Pan , Chiakang Sung , Joseph Huang , Bonnie Wang , Khai Nguyen , Xiaobao Wang , Gopinath Rangan , In Whan Kim , Yan Chong
IPC分类号： G11C8/00
CPC分类号： H03K19/1776 , G11C8/16
摘要： Methods and apparatus for a dual-port SRAM in a programmable logic device. One embodiment provides a programmable logic integrated circuit including a dual-port memory. The memory includes a plurality of memory storage cells, and each memory storage cell has a memory cell having a first node and a second node, a first series of devices connected between a first data line and the first node of the memory cell, and a second series of devices connected between a second data line and the second node of the memory cell. A read cell is connected to the second node of the memory cell. A word line is connected to a first device in the first series of devices, a second device in the second series of devices, and the read cell.

20. 发明授权

US06961280B1 Techniques for implementing address recycling in memory circuits 失效
标题翻译：在存储器电路中实现地址回收的技术
公开(公告)号：US06961280B1
公开(公告)日：2005-11-01
申请号：US10731279
申请日：2003-12-08
申请人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Johnson Tan
发明人： Philip Pan , Chiakang Sung , Joseph Huang , Yan Chong , Johnson Tan
IPC分类号： G06F12/08 , G11C8/00 , G11C8/06 , G11C8/10
CPC分类号： G11C8/06 , G06F12/0895 , G11C8/10
摘要： Techniques are provided for recycling addresses in memory blocks. Address signals in memory blocks are stored temporarily in a set of parallel coupled address registers. The address registers transfer the address signals to an address decoder block, which decodes the address signals. The address decoder block transfers the decoded addresses to a memory array. A stall state occurs when the cache memory block needs a new set of data to replace the old set of data. Address signals are stored in the address registers during the stall state by coupling each register's output to its data input using a series of multiplexers. The multiplexers are controlled by an address stall signal that indicates the onset and the end of a stall state. After the end of a stall state, the address registers store the next address signal received at the memory block.
摘要翻译：提供技术来回收内存块中的地址。存储器块中的地址信号被临时存储在一组并行耦合的地址寄存器中。地址寄存器将地址信号传送到地址解码块，对地址信号进行解码。地址解码器块将解码的地址传送到存储器阵列。当缓存存储块需要一组新的数据来替换旧的数据集时，会发生停顿状态。通过使用一系列多路复用器将每个寄存器的输出耦合到其数据输入，地址信号在失速状态下存储在地址寄存器中。多路复用器由指示失速状态的开始和结束的地址停止信号控制。在停止状态结束后，地址寄存器存储在存储块处接收的下一个地址信号。

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