专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08217383B2 High hole mobility p-channel Ge transistor structure on Si substrate 有权
标题翻译：硅衬底上的高空穴迁移率p沟道Ge晶体管结构
公开(公告)号：US08217383B2
公开(公告)日：2012-07-10
申请号：US12876922
申请日：2010-09-07
申请人： Mantu K. Hudait , Suman Datta , Jack T. Kavalieros , Peter G. Tolchinsky
发明人： Mantu K. Hudait , Suman Datta , Jack T. Kavalieros , Peter G. Tolchinsky
IPC分类号： H01L29/775 , H01L29/20
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02505 , H01L21/02546 , H01L21/02573 , H01L21/0262 , H01L29/267 , H01L29/66431
摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

12. 发明申请

US20120142166A1 STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI 失效
标题翻译：堆叠故障和用于集成III-V的双阻塞器
公开(公告)号：US20120142166A1
公开(公告)日：2012-06-07
申请号：US13366143
申请日：2012-02-03
申请人： Mantu K. Hudait , Mohamad A. Shaheen , Loren A. Chow , Peter G. Tolchinsky , Joel M. Fastenau , Dmitri Loubychev , Amy W.K. Liu
发明人： Mantu K. Hudait , Mohamad A. Shaheen , Loren A. Chow , Peter G. Tolchinsky , Joel M. Fastenau , Dmitri Loubychev , Amy W.K. Liu
IPC分类号： H01L21/20
CPC分类号： H01L29/7785 , H01L21/02381 , H01L21/02433 , H01L21/02466 , H01L21/02549 , H01L21/02617 , H01L29/66462
摘要： A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.
摘要翻译：描述了在硅衬底上形成III-V器件层的层叠故障和双阻挡屏障及其制造方法。本发明的实施方案能够在硅衬底上形成缺陷密度低于1×108cm-2的III-V InSb器件层。在本发明的实施例中，缓冲层位于III-V器件层和硅衬底之间以滑动位错。在本发明的一个实施例中，基于晶格常数，带隙和熔点选择GaSb缓冲层，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。在具体实施例中，III-V InSb器件层直接形成在GaSb缓冲器上。

13. 发明授权

US07851781B2 Buffer layers for device isolation of devices grown on silicon 有权
标题翻译：用于在硅上生长的器件隔离的缓冲层
公开(公告)号：US07851781B2
公开(公告)日：2010-12-14
申请号：US12378407
申请日：2009-02-13
申请人： Mantu K. Hudait , Mohamad A. Shaheen , Loren A. Chow , Peter G. Tolchinsky , Joel M. Fastenau , Dmitri Loubychev , Amy W. K. Liu
发明人： Mantu K. Hudait , Mohamad A. Shaheen , Loren A. Chow , Peter G. Tolchinsky , Joel M. Fastenau , Dmitri Loubychev , Amy W. K. Liu
IPC分类号： H01L31/00
CPC分类号： H01L29/7784 , H01L21/02381 , H01L21/02433 , H01L21/02466 , H01L21/02502 , H01L21/02505 , H01L21/02549 , H01L29/045 , H01L29/201 , H01L29/205 , H01L29/66462
摘要： Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.
摘要翻译：各种实施例提供了在硅衬底上生长的缓冲层，其为相对于III-V材料器件层（例如基于InSb的器件）形成的器件以及在硅衬底上生长的体薄膜提供期望的器件隔离。此外，缓冲层可以减轻晶体管器件和硅衬底之间的并联传导问题。此外，缓冲层解决了薄膜相对于其形成晶体管和硅衬底之间的晶格失配。

14. 发明申请

US20090315018A1 Methods of forming buffer layer architecture on silicon and structures formed thereby 失效
标题翻译：在硅上形成缓冲层结构的方法和由此形成的结构
公开(公告)号：US20090315018A1
公开(公告)日：2009-12-24
申请号：US12214737
申请日：2008-06-19
申请人： Mantu K. Hudait , Peter G. Tolchinsky , Loren A. Chow , Dmitri Loubychev , Joel M. Fastenau , Amy W.K. Liu
发明人： Mantu K. Hudait , Peter G. Tolchinsky , Loren A. Chow , Dmitri Loubychev , Joel M. Fastenau , Amy W.K. Liu
IPC分类号： H01L29/12 , H01L21/205
CPC分类号： H01L21/02546 , B82Y10/00 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/0251 , H01L29/127 , H01L29/205 , H01L29/66462
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an In0.52Al0.48As bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InxAl1-xAs layer on the In0.52Al0.48As bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在衬底上形成GaSb成核层，在GaSb成核层上形成Ga（Al）AsSb缓冲层，在Ga（Al）AsSb缓冲层上形成In0.52Al0.48As底部阻挡层，并形成因此In0.52Al0.48As底部阻挡层上的渐变InxAl1-xAs层因此能够制造低缺陷，基于器件级InGaAs的量子阱结构。

15. 发明申请

US20090071918A1 VERTICAL SEMICONDUCTOR WAFER CARRIER 审中-公开
标题翻译：垂直半导体波导载体
公开(公告)号：US20090071918A1
公开(公告)日：2009-03-19
申请号：US11857398
申请日：2007-09-18
申请人： Panchapakesan Ramanarayanan , Karson Knutson , Peter G. Tolchinsky , Christopher Parker
发明人： Panchapakesan Ramanarayanan , Karson Knutson , Peter G. Tolchinsky , Christopher Parker
IPC分类号： H01L21/00
CPC分类号： H01L21/67309 , H01L21/6732
摘要： A vertical semiconductor wafer carrier comprises a circular base, a first wafer support rod mounted at a first position proximate a perimeter of the circular base, a second wafer support rod mounted at a second position proximate the perimeter of the circular base, wherein an angle θ12 formed between the first position and the second position relative to a center of the circular base is around 20°, a third wafer support rod mounted at a third position proximate the perimeter of the circular base, and a fourth wafer support rod mounted at a fourth position proximate the perimeter of the circular base, wherein an angle θ34 formed between the third position and the fourth position relative to the center of the circular base is around 20°, and wherein an angle θ14 formed between the first and fourth positions relative to the center of the circular base is around 180°.
摘要翻译：垂直半导体晶片载体包括圆形基底，安装在靠近圆形基底的周边的第一位置处的第一晶片支撑杆，安装在靠近圆形基底的周边的第二位置处的第二晶片支撑杆，其中角度θ12 形成在第一位置和第二位置之间相对于圆形基座的中心约为20°，第三晶片支撑杆安装在靠近圆形基座周边的第三位置，第四晶片支撑杆安装在第四位置位于邻近圆形底座的周边的位置，其中形成在第三位置和第四位置之间的相对于圆形底座的中心的角度θ34大约为20°，并且其中形成在第一和第四位置之间的角度θ14相对于圆形基座的中心约为180°。

16. 发明授权

US09559160B2 Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition 有权
标题翻译：具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件
公开(公告)号：US09559160B2
公开(公告)日：2017-01-31
申请号：US13996506
申请日：2011-12-23
申请人： Annalisa Cappellani , Peter G. Tolchinsky , Kelin J. Kuhn , Glenn A. Glass , Van H. Le
发明人： Annalisa Cappellani , Peter G. Tolchinsky , Kelin J. Kuhn , Glenn A. Glass , Van H. Le
IPC分类号： H01L29/04 , H01L29/66 , H01L29/775 , H01L27/12 , B82Y10/00 , B82Y40/00 , H01L29/06 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/045 , B82Y10/00 , B82Y40/00 , H01L21/823821 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78687 , H01L29/78696
摘要： Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
摘要翻译：描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料组成。通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座，将第二纳米线或半导体本体与晶体衬底隔离。

17. 发明申请

US20130320294A1 COMMON-SUBSTRATE SEMICONDUCTOR DEVICES HAVING NANOWIRES OR SEMICONDUCTOR BODIES WITH DIFFERING MATERIAL ORIENTATION OR COMPOSITION 有权
标题翻译：具有不同材料取向或组成的纳米线或半导体器件的共面衬底半导体器件
公开(公告)号：US20130320294A1
公开(公告)日：2013-12-05
申请号：US13996506
申请日：2011-12-23
申请人： Annalisa Cappellani , Peter G. Tolchinsky , Kelin J. Kuhn , Glenn A. Glass , Van H. Le
发明人： Annalisa Cappellani , Peter G. Tolchinsky , Kelin J. Kuhn , Glenn A. Glass , Van H. Le
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , B82Y10/00 , B82Y40/00 , H01L21/823821 , H01L27/0924 , H01L27/1211 , H01L29/0649 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78687 , H01L29/78696
摘要： Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
摘要翻译：描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料组成。通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座将第二纳米线或半导体本体与晶体衬底隔离。

18. 发明授权

US07863710B2 Dislocation removal from a group III-V film grown on a semiconductor substrate 有权
标题翻译：从在半导体衬底上生长的III-V族膜剥离
公开(公告)号：US07863710B2
公开(公告)日：2011-01-04
申请号：US12032579
申请日：2008-02-15
申请人： Mantu K. Hudait , Peter G. Tolchinsky , Jack T. Kavalieros , Marko Radosavljevic
发明人： Mantu K. Hudait , Peter G. Tolchinsky , Jack T. Kavalieros , Marko Radosavljevic
IPC分类号： H01L29/20
CPC分类号： H01L21/02664 , H01L21/02381 , H01L21/02433 , H01L21/02461 , H01L21/02463 , H01L21/02532 , H01L21/02546 , H01L21/02549 , H01L21/02686 , H01L21/268
摘要： Dislocation removal from a group III-V film grown on a semiconductor substrate is generally described. In one example, an apparatus includes a semiconductor substrate, a buffer film including a group III-V semiconductor material epitaxially coupled to the semiconductor substrate wherein the buffer film includes material melted by laser pulse irradiation and recrystallized to substantially remove dislocations or defects from the buffer film, and a first semiconductor film epitaxially grown on the buffer film wherein a lattice mismatch exists between the semiconductor substrate and the first semiconductor film.
摘要翻译：通常描述从在半导体衬底上生长的III-V族膜脱离脱落。在一个示例中，一种装置包括半导体衬底，包括外延耦合到半导体衬底的III-V族半导体材料的缓冲膜，其中缓冲膜包括通过激光脉冲照射熔化的材料并重结晶以基本上从缓冲器中去除位错或缺陷膜，以及在所述缓冲膜上外延生长的第一半导体膜，其中在所述半导体衬底和所述第一半导体膜之间存在晶格失配。

19. 发明授权

US07687799B2 Methods of forming buffer layer architecture on silicon and structures formed thereby 失效
标题翻译：在硅上形成缓冲层结构的方法和由此形成的结构
公开(公告)号：US07687799B2
公开(公告)日：2010-03-30
申请号：US12214737
申请日：2008-06-19
申请人： Mantu K. Hudait , Peter G. Tolchinsky , Loren A. Chow , Dmitri Loubychev , Joel M. Fastenau , Amy W. K. Liu
发明人： Mantu K. Hudait , Peter G. Tolchinsky , Loren A. Chow , Dmitri Loubychev , Joel M. Fastenau , Amy W. K. Liu
IPC分类号： H01L31/00 , H01L21/338
CPC分类号： H01L21/02546 , B82Y10/00 , H01L21/02381 , H01L21/02433 , H01L21/02463 , H01L21/02466 , H01L21/02505 , H01L21/0251 , H01L29/127 , H01L29/205 , H01L29/66462
摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an In0.52Al0.48As bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InxAl1-xAs layer on the In0.52Al0.48As bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.
摘要翻译：描述形成微电子器件的方法和相关结构。这些方法可以包括在衬底上形成GaSb成核层，在GaSb成核层上形成Ga（Al）AsSb缓冲层，在Ga（Al）AsSb缓冲层上形成In0.52Al0.48As底部阻挡层，并形成因此In0.52Al0.48As底部阻挡层上的渐变InxAl1-xAs层因此能够制造低缺陷，基于器件级InGaAs的量子阱结构。

20. 发明申请

US20100148153A1 Group III-V devices with delta-doped layer under channel region 审中-公开
标题翻译： III-V族III族掺杂层在通道区下面
公开(公告)号：US20100148153A1
公开(公告)日：2010-06-17
申请号：US12316878
申请日：2008-12-16
申请人： Mantu K. Hudait , Peter G. Tolchinsky , Robert S. Chau , Marko Radosavljevic , Ravi Pillarisetty , Aaron A. Budrevich
发明人： Mantu K. Hudait , Peter G. Tolchinsky , Robert S. Chau , Marko Radosavljevic , Ravi Pillarisetty , Aaron A. Budrevich
IPC分类号： H01L29/78
CPC分类号： H01L29/7784 , H01L29/365 , H01L29/66462
摘要： A group III-V material device has a delta-doped region below a channel region. This may improve the performance of the device by reducing the distance between the gate and the channel region.
摘要翻译： III-V族材料器件在沟道区域下方具有δ掺杂区域。这可以通过减小栅极和沟道区域之间的距离来改善器件的性能。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式