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11. 发明授权

US5670417A Method for fabricating self-aligned semiconductor component 失效
标题翻译：制造自对准半导体部件的方法
公开(公告)号：US5670417A
公开(公告)日：1997-09-23
申请号：US622535
申请日：1996-03-25
申请人： Charles T. Lambson , Paul W. Sanders
发明人： Charles T. Lambson , Paul W. Sanders
IPC分类号： H01L21/331 , H01L21/225
CPC分类号： H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A self-aligned semiconductor component (10) includes a layer (14) having two openings (36, 38) and overlying a doped region (13) in a substrate (11). One (36) of the two openings (36, 38) is used to self-align a different doped region (22) and a portion (27) of an electrode (27, 31). The electrode (27, 31) has another portion (31) overlying the self-aligned portion (27) to increase the current carrying capacity of the electrode (27, 31). A different electrode is formed in the other one (38) of the two openings (36, 38) and has a smaller current carrying capacity than the other electrode (27, 31).
摘要翻译：自对准半导体部件（10）包括具有两个开口（36,38）并且覆盖衬底（11）中的掺杂区域（13）的层（14）。两个开口（36,38）中的一个（36）用于自对准不同的掺杂区域（22）和电极（27,31）的部分（27）。电极（27,31）具有覆盖自对准部分（27）的另一部分（31），以增加电极（27,31）的载流能力。在两个开口（36,38）中的另一个（38）中形成不同的电极，并且具有比另一个电极（27,31）更小的载流能力。

12. 发明授权

US5139959A Method for forming bipolar transistor input protection 失效
标题翻译：形成双极晶体管输入保护的方法
公开(公告)号：US5139959A
公开(公告)日：1992-08-18
申请号：US822804
申请日：1992-01-21
申请人： Scott L. Craft , Stephen P. Robb , Paul W. Sanders
发明人： Scott L. Craft , Stephen P. Robb , Paul W. Sanders
IPC分类号： H01L27/02
CPC分类号： H01L29/7302 , H01L27/0248 , H01L29/0692 , Y10S148/011
摘要： A protective circuit for an input to a bipolar transistor (10) capable of operating in the microwave frequency range. In a first embodiment, a polysilicon diode (24) is connected across a base-emitter junction of the bipolar transistor (10). In a second embodiment, a polysilicon resistor (38) is connected in series with an emitter of the bipolar transistor (10), and the polysilicon diode (24) is connected across the series combination of the base-emitter junction and the polysilicon resistor (38). The layout of the transistor (10) and the islands of polysilicon (23, 25) housing the diode is critical since the bipolar transistor (10) is capable of operating in the microwave frequency range. In a first layout, an island of polysilicon (25) is centered between two transistor regions (47 and 48). In an exterior diode layout, a transistor region (51) is centered between two islands of polysilicon (23 and 25).
摘要翻译：一种用于能够在微波频率范围内工作的双极晶体管（10）的输入的保护电路。在第一实施例中，多晶硅二极管（24）跨越双极晶体管（10）的基极 - 发射极结连接。在第二实施例中，多晶硅电阻器（38）与双极晶体管（10）的发射极串联连接，并且多晶硅二极管（24）跨越基极 - 发射极结和多晶硅电阻器的串联组合 38）。晶体管（10）的布局和容纳二极管的多晶硅岛（23,25）的关键是至关重要的，因为双极晶体管（10）能够在微波频率范围内工作。在第一布局中，多晶硅岛（25）在两个晶体管区域（47和48）之间居中。在外部二极管布局中，晶体管区域（51）在两个多晶硅岛（23和25）之间居中。

13. 发明申请

US20130099312A1 SEMICONDUCTOR STRUCTURE HAVING A THROUGH SUBSTRATE VIA (TSV) AND METHOD FOR FORMING 有权
标题翻译：具有通过（TSV）的基底的半导体结构和形成方法
公开(公告)号：US20130099312A1
公开(公告)日：2013-04-25
申请号：US13279776
申请日：2011-10-24
申请人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
发明人： Thuy B. Dao , Joel E. Keys , Hernan A. Rueda , Paul W. Sanders
IPC分类号： H01L29/78 , H01L21/225
CPC分类号： H01L21/76898 , H01L21/26586 , H01L23/5227 , H01L23/66 , H01L28/10 , H01L29/4175 , H01L29/41766 , H01L29/456 , H01L29/66659 , H01L29/7835 , H01L29/868 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device structure includes a substrate having a background doping of a first concentration and of a first conductivity type. A through substrate via (TSV) is through the substrate. A device has a first doped region of a second conductivity on a first side of the substrate. A second doped region is around the TSV. The second doped region has a doping of a second concentration greater than the first concentration and is of the first conductivity type.
摘要翻译：半导体器件结构包括具有第一浓度和第一导电类型的背景掺杂的衬底。贯穿基板通孔（TSV）通过基板。器件在衬底的第一侧上具有第二导电性的第一掺杂区域。第二掺杂区域在TSV周围。第二掺杂区具有大于第一浓度的第二浓度的掺杂并且是第一导电类型。

14. 发明授权

US08344503B2 3-D circuits with integrated passive devices 有权
标题翻译：具有集成无源器件的3-D电路
公开(公告)号：US08344503B2
公开(公告)日：2013-01-01
申请号：US12277519
申请日：2008-11-25
申请人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L23/34
CPC分类号： H01L25/162 , H01L21/6835 , H01L21/76898 , H01L23/3675 , H01L23/481 , H01L23/5384 , H01L23/58 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0296 , H01L27/0629 , H01L28/00 , H01L2221/6835 , H01L2221/68381 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/1147 , H01L2224/13009 , H01L2224/13025 , H01L2224/13147 , H01L2224/16503 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2224/83365 , H01L2224/83385 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2224/81 , H01L2224/13099
摘要： 3-D ICs (18, 18′, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20). The isolator substrate (30) provides superior IPD (38) to AD (26) cross-talk attenuation while permitting each substrate (20, 30, 34) to have small high aspect ratio TSVs (40), facilitating high circuit packing density and efficient manufacturing.
摘要翻译：通过堆叠单独预制的基板（20,30,34），通过穿通基板（20,30,34）耦合而提供具有降低的串扰和高封装密度的集成无源器件（IPD）（38）的3-D IC（18,18'，90） -vias（TSV）（40）。有源器件（AD）衬底（20）在其上部（26）上具有接触。隔离器基板（30）接合到AD基板（20），使得隔离器基板（30）中的TSV（4030）与AD基板（20）上的触点（26）相连，并且希望具有互连区（44）在其上表面。 IPD衬底（34）被结合到隔离器衬底（30），使得其中的TSV（4034）耦合到隔离器衬底（30）上的互连区（44）和/或其中的TSV（4030）。 IPD（38）形成在其上表面上，并由IPD（34）和隔离器（30）衬底中的TSV（4034,4030）与AD衬底（20）中的器件（26）耦合。隔离器基板（30）提供优异的IPD（38）到AD（26）串扰衰减，同时允许每个基板（20,30,34）具有小的高纵横比TSV（40），有利于高电路封装密度和效率制造业。

15. 发明授权

US08062975B2 Through substrate vias 有权
标题翻译：通过衬底通孔
公开(公告)号：US08062975B2
公开(公告)日：2011-11-22
申请号：US12425159
申请日：2009-04-16
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20′) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30′) of a first aspect ratio containing first conductors (36, 36′) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22″) from the rear surface (22) to form a modified wafer (20′) of smaller final thickness (21′) with a new rear surface (22′), and (iii) forming from the new rear surface (22′), much deeper vias (40, 40′) of second aspect ratios beneath the device region (26) with second conductors (56, 56′) therein contacting the first conductors (36, 36′), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在通过以下方式形成靠近基板晶片（20,20'）的前表面（23）的第一厚度（27）的器件区域（26）所需的基本上所有高温操作之后提供穿过衬底通孔（TSV）：（ i）从前表面（23）形成第一纵横比比较浅的通孔（30,30'），该第一纵横比包含优选地延伸穿过第一厚度（27）但不延伸穿过初始晶片的第一导体（36,36'） 20）厚度（21），（ii）从后表面（22）去除材料（22“）以形成具有新的后表面（22'）的较小最终厚度（21'）的改性晶片（20'），和（iii）从新的后表面（22'）形成在装置区域（26）下面的第二高宽比的更深的通孔（40,40'），其中第二导体（56,56'）在其中接触第一导体 36，36'），从而在制造和器件区域中基本上不影响晶片坚固性，从而提供前后互连区域。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

16. 发明申请

US20100127345A1 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES 有权
标题翻译：具有集成无源器件的3-D电路
公开(公告)号：US20100127345A1
公开(公告)日：2010-05-27
申请号：US12277519
申请日：2008-11-25
申请人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Robert E. Jones , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L29/00 , H01L21/60
CPC分类号： H01L25/162 , H01L21/6835 , H01L21/76898 , H01L23/3675 , H01L23/481 , H01L23/5384 , H01L23/58 , H01L24/05 , H01L24/11 , H01L24/16 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L27/0296 , H01L27/0629 , H01L28/00 , H01L2221/6835 , H01L2221/68381 , H01L2224/0401 , H01L2224/05552 , H01L2224/0557 , H01L2224/1147 , H01L2224/13009 , H01L2224/13025 , H01L2224/13147 , H01L2224/16503 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2224/83365 , H01L2224/83385 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2225/06572 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01018 , H01L2924/01021 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2224/81 , H01L2224/13099
摘要： 3-D ICs (18, 18′, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20). The isolator substrate (30) provides superior IPD (38) to AD (26) cross-talk attenuation while permitting each substrate (20, 30, 34) to have small high aspect ratio TSVs (40), facilitating high circuit packing density and efficient manufacturing.
摘要翻译：通过堆叠单独预制的基板（20,30,34），通过穿通基板（20,30,34）耦合而提供具有降低的串扰和高封装密度的集成无源器件（IPD）（38）的3-D IC（18,18'，90） -vias（TSV）（40）。有源器件（AD）衬底（20）在其上部（26）上具有接触。隔离器基板（30）接合到AD基板（20），使得隔离器基板（30）中的TSV（4030）与AD基板（20）上的触点（26）相连，并且希望具有互连区（44）在其上表面。 IPD衬底（34）被结合到隔离器衬底（30），使得其中的TSV（4034）耦合到隔离器衬底（30）上的互连区（44）和/或其中的TSV（4030）。 IPD（38）形成在其上表面上，并且在IPD（34）和隔离器（30）衬底中的TSV（4034,4030）与AD衬底（20）中的器件（26）耦合。隔离器基板（30）提供优异的IPD（38）到AD（26）串扰衰减，同时允许每个基板（20,30,34）具有小的高纵横比TSV（40），有利于高电路封装密度和效率制造业。

17. 发明授权

US5134448A MOSFET with substrate source contact 失效
标题翻译： MOSFET与衬底源接触
公开(公告)号：US5134448A
公开(公告)日：1992-07-28
申请号：US643636
申请日：1991-01-22
申请人： Robert J. Johnsen , Paul W. Sanders
发明人： Robert J. Johnsen , Paul W. Sanders
IPC分类号： H01L21/336 , H01L21/74 , H01L29/10 , H01L29/41 , H01L29/423 , H01L29/78
CPC分类号： H01L29/1095 , H01L21/743 , H01L29/41 , H01L29/781 , H01L29/7813 , H01L29/42368
摘要： A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-, P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.
摘要翻译：具有背侧源极接触和顶侧栅极和漏极接触的MOSFET由包括叠置在半导体管芯的顶表面和底表面之间的N +，N-，P-，N +区域的结构提供。在优选的实施方案中，从顶表面到P，N +界面蚀刻两个沟槽。在一个沟槽中设置埋置的P-，N +短路，并且在暴露在另一个沟槽中的侧壁P-区域上设置栅极电介质和栅电极。这产生了垂直MOSFET，其中N +衬底形成与由栅极产生沟道的P-体区域短路的源极区域。在RF接地源电路应用中获得了卓越的性能。

18. 发明授权

US5023196A Method for forming a MOSFET with substrate source contact 失效
标题翻译：用于形成具有衬底源极接触的MOSFET的方法
公开(公告)号：US5023196A
公开(公告)日：1991-06-11
申请号：US471899
申请日：1990-01-29
申请人： Robert J. Johnsen , Paul W. Sanders
发明人： Robert J. Johnsen , Paul W. Sanders
IPC分类号： H01L21/336 , H01L21/74 , H01L29/10 , H01L29/41 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/743 , H01L29/1095 , H01L29/41 , H01L29/781 , H01L29/42368 , Y10S148/168
摘要： A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-,P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

19. 发明授权

US4202005A Distributed collector ballast resistor structure 失效
标题翻译：分布式集电极镇流电阻结构
公开(公告)号：US4202005A
公开(公告)日：1980-05-06
申请号：US962122
申请日：1978-11-20
申请人： Paul W. Sanders
发明人： Paul W. Sanders
IPC分类号： H01L27/07 , H01L29/08 , H01L29/73 , H01L27/02
CPC分类号： H01L29/0821 , H01L27/0772 , H01L29/7304
摘要： A distributed collector ballast resistor structure for use in a distributed collector contacted transistor comprises a diffusion geometry which is designed to employ a number of distributed collector ballast resistors in parallel as opposed to a single bulk resistor in series with the collector circuit thereby generating a lower current for a given voltage during avalanche while allowing lower saturation voltage, better RF gain and higher saturated output power.
摘要翻译：用于分布式集电极接触晶体管的分布式集电极镇流电阻器结构包括扩散几何形状，其被设计为并联使用多个分布式集电极镇流电阻器，而不是与集电极电路串联的单个体电阻器，从而产生较低的电流对于雪崩期间的给定电压，同时允许较低的饱和电压，更好的RF增益和更高的饱和输出功率。

20. 发明授权

US08329579B2 Through substrate VIAS 有权
标题翻译：通过基底VIAS
公开(公告)号：US08329579B2
公开(公告)日：2012-12-11
申请号：US13188084
申请日：2011-07-21
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L21/44 , H01L23/04
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在基本上所有的高温操作之后提供通过衬底通孔（TSV），所述高温操作是通过以下步骤形成靠近衬底晶片的前表面的第一厚度的器件区域：（i）从前表面形成第一方面的较浅的通孔比例包含优选地穿过第一厚度而不是通过初始晶片厚度的第一导体，（ii）从后表面去除材料以形成具有新的后表面的较小最终厚度的改性晶片，以及（iii）从新的后表面，在器件区域下方的第二宽高比的深度更深的通孔，其中其中第二导体接触第一导体，从而在制造和器件区域区域中基本上不影响晶片坚固性而提供前后互连。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

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