专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07099203B1 Circuit and method for writing a binary value to a memory cell 失效
标题翻译：将二进制值写入存储单元的电路和方法
公开(公告)号：US07099203B1
公开(公告)日：2006-08-29
申请号：US11057281
申请日：2005-02-11
申请人： Paul A. Bunce , John D. Davis , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Donald W. Plass
IPC分类号： G11C7/10 , G11C11/00
CPC分类号： G11C7/22 , G11C2207/2263
摘要： A circuit and a method for writing a binary value to a memory cell are provided. The circuit includes a first field-effect transistor having a first drain, a first drain, and a first gate operably coupled between the first drain and the first source. The first drain is operably coupled to a first memory cell. The first gate configured to receive a first data signal. The circuit further includes a second field-effect transistor having a second drain, a second source, and a second gate operably coupled between the second drain and the second source. The drain source is operably coupled to the first memory cell. The second gate is configured to receive a second data signal. The circuit further includes a first signal inverter having a first input terminal and a first output terminal. The first output terminal is operably coupled to both of the first and second sources. The first signal inverter is configured to output a first control signal on the first output terminal when the first input terminal receives a second control signal. When the first control signal has a second logic level and the first data signal has a first logic level and the second data signal has the second logic level, the first and second field-effect transistors induce the first memory cell to store a first binary value.
摘要翻译：提供了一种将二进制值写入存储单元的电路和方法。电路包括具有第一漏极，第一漏极和第一栅极的第一场效应晶体管，其可操作地耦合在第一漏极和第一源极之间。第一漏极可操作地耦合到第一存储器单元。第一门被配置为接收第一数据信号。电路还包括第二场效应晶体管，其具有可操作地耦合在第二漏极和第二源之间的第二漏极，第二源极和第二栅极。漏源可操作地耦合到第一存储单元。第二门被配置为接收第二数据信号。电路还包括具有第一输入端和第一输出端的第一信号反相器。第一输出端子可操作地耦合到第一和第二源两者。第一信号反相器被配置为当第一输入端子接收到第二控制信号时，在第一输出端子上输出第一控制信号。当第一控制信号具有第二逻辑电平且第一数据信号具有第一逻辑电平且第二数据信号具有第二逻辑电平时，第一和第二场效应晶体管感应第一存储器单元以存储第一二进制值。

12. 发明授权

US07688650B2 Write control method for a memory array configured with multiple memory subarrays 失效
标题翻译：用多个存储器子阵列配置的存储器阵列的写控制方法
公开(公告)号：US07688650B2
公开(公告)日：2010-03-30
申请号：US12139675
申请日：2008-06-16
申请人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G11C7/00 , G11C7/22
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

13. 发明授权

US07471590B2 Write control circuitry and method for a memory array configured with multiple memory subarrays 失效
标题翻译：用于配置有多个存储器子阵列的存储器阵列的写控制电路和方法
公开(公告)号：US07471590B2
公开(公告)日：2008-12-30
申请号：US11762833
申请日：2007-06-14
申请人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J Reyer
发明人： John D. Davis , Paul A. Bunce , Donald W. Plass , Kenneth J Reyer
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , G11C7/18
摘要： Write control circuitry and control method are provided for a memory array configured with multiple memory subarrays. The write control circuitry includes multiple subarray write controllers associated with the multiple memory subarrays, each subarray write controller selectively enabling a local write control signal to its associated memory subarray. The selectively enabling is responsive to a received subarray select signal, wherein only one subarray select signal is active at a time. At least some subarray write controllers are powered at least in part via a switched power node, wherein powering of the switched power node is distributively implemented among the subarray write controllers. In one example, the distributively implemented powering of the switched power node is accomplished via multiple inverters distributed among the subarray write controllers, each inverter having an output coupled to the switched power node, and an input coupled to receive a global write enable signal.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供写控制电路和控制方法。写控制电路包括与多个存储器子阵列相关联的多个子阵列写控制器，每个子阵列写控制器选择性地使本地写控制信号到其相关的存储器子阵列。选择性地使能响应于接收的子阵列选择信号，其中一次只有一个子阵列选择信号是有效的。至少一些子阵列写控制器至少部分地通过交换式电源节点供电，其中，在子阵列写入控制器之间分配地实现切换的功率节点的供电。在一个示例中，通过分布在子阵列写控制器之间的多个反相器实现开关电源节点的分布式实现的供电，每个反相器具有耦合到开关电源节点的输出，以及耦合以接收全局写使能信号的输入。

14. 发明授权

US07088638B1 Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays 失效
标题翻译：用于配置有多个内存子阵列的内存阵列的全局和本地读取控制同步方法和系统
公开(公告)号：US07088638B1
公开(公告)日：2006-08-08
申请号：US11054176
申请日：2005-02-09
申请人： Paul A. Bunce , John D. Davis , James W. Dawson , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , James W. Dawson , Donald W. Plass
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A global and local read control synchronization method and system are provided for a memory array configured with multiple memory subarrays. Address signals are decoded to activate based thereon subarray select signals and a cumulative subarray select signal. The cumulative subarray select signal goes active whenever a subarray select signal goes active, and therefore, each pulse of the cumulative subarray select signal is synchronous with one pulse of the subarray select signals. Local read control signals for the multiple memory subarrays are obtained employing the subarray select signals, and at least one global read control signal for the memory array is obtained employing the cumulative subarray select signal. In one example, the memory array has a hierarchical bitline architecture.
摘要翻译：为配置有多个存储器子阵列的存储器阵列提供全局和本地读取控制同步方法和系统。解码地址信号以基于子阵列选择信号和累积子阵列选择信号来激活。每当子阵列选择信号变为有效时，累积子阵列选择信号变为有效，因此累积子阵列选择信号的每个脉冲与子阵列选择信号的一个脉冲同步。使用子阵列选择信号获得用于多个存储器子阵列的本地读取控制信号，并且使用累积子阵列选择信号获得用于存储器阵列的至少一个全局读取控制信号。在一个示例中，存储器阵列具有分层位线架构。

15. 发明授权

US07009895B2 Method for skip over redundancy decode with very low overhead 有权
标题翻译：用于以非常低的开销跳过冗余解码的方法
公开(公告)号：US07009895B2
公开(公告)日：2006-03-07
申请号：US10814719
申请日：2004-03-31
申请人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/806 , G11C29/848
摘要： The method described uses a Skip-Over technique which requires a set of muxes at the input and output of a block that is to be repaired. The improved method of implementing I/O redundancy control logic has a minimal impact to both chip area and chip wire tracks. To overcome problems of required real estate usage on a chip that was undesirable enables use of odd and even decoder outputs that can share a single wire track, the same wire being utilizable for both odd and even decoder outputs. In order to implement the decode and carry function as a centralized function, there arises a requirement that logically adjacent decode circuits (decoders connected by a carry signal) should be physically close together to minimize the overhead of the carry wiring. If the decode structure and the mux structure are arranged orthogonal to each other, then each decoder output would require a wire track. The described method however, allows odd and even decoder outputs to share the same wire track. This reduces the number of wire tracks from 1 track per I/O to 1 track per 2 I/Os.
摘要翻译：所描述的方法使用跳过技术，其需要在待修复的块的输入和输出处的一组复用器。实现I / O冗余控制逻辑的改进方法对芯片面积和芯片线轨都具有最小的影响。为了克服在不期望的芯片上所需的房地产使用的问题，可以使用可以共享单个线路的奇数和偶数解码器输出，同样的线可用于奇数和偶数解码器输出。为了实现作为集中功能的解码和携带功能，出现了逻辑上相邻的解码电路（通过进位信号连接的解码器）应物理上靠近在一起以最小化进位线路开销的要求。如果解码结构和多路复用结构彼此正交配置，则每个解码器输出将需要线轨。然而，所描述的方法允许奇数和偶数解码器输出共享相同的线轨道。这减少了每个I / O从1个磁道到每2个I / O到1个磁道的电线轨迹数量。

16. 发明授权

US06584023B1 System for implementing a column redundancy scheme for arrays with controls that span multiple data bits 失效
标题翻译：用于实现具有跨多个数据位的控件的数组的列冗余方案的系统
公开(公告)号：US06584023B1
公开(公告)日：2003-06-24
申请号：US10043024
申请日：2002-01-09
申请人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
发明人： Paul A. Bunce , John D. Davis , Thomas J. Knips , Donald W. Plass
IPC分类号： G11C700
CPC分类号： G11C29/808 , G11C29/848
摘要： An exemplary embodiment of the present invention is a system for implementing a column redundancy scheme for arrays with controls that span multiple data bits. The system includes an array of data bits for receiving data inputs, a spare data bit and a field control input line. Also included in the system is circuitry to separate a field control signal from the field control input line into one or more individual control signals for activating a corresponding data bit in the array or for input to a multiplexor. The system further comprises circuitry to steer around a defective data bit in the array. This circuitry includes: a field control signal multiplexor corresponding to each field control signal; a spare control signal multiplexor to activate the spare data bit; a data multiplexor corresponding to each of the data bits in the array; and a spare data multiplexor to steer one of the data inputs to the spare data bit. The system also includes programmable logic in communication with the field control signal multiplexor, the spare control signal multiplexor, the data multiplexor and the spare data multiplexor to cause the steer around to take place in response to detecting a defective data bit in the array.
摘要翻译：本发明的示例性实施例是用于对具有跨越多个数据位的控制的阵列实现列冗余方案的系统。该系统包括用于接收数据输入的数据位阵列，备用数据位和场控制输入线。还包括在系统中的电路是将场控制信号与场控制输入线分离成一个或多个单独的控制信号，用于激活阵列中相应的数据位或输入到多路复用器。该系统还包括用于控制阵列中的有缺陷的数据位的电路。该电路包括：对应于每个场控制信号的场控制信号多路复用器; 备用控制信号多路复用器，用于激活备用数据位; 与阵列中的每个数据位相对应的数据多路复用器; 以及备用数据多路复用器，以将数据输入中的一个引导到备用数据位。该系统还包括与现场控制信号多路复用器，备用控制信号多路复用器，数据多路复用器和备用数据多路复用器通信的可编程逻辑，以响应于检测到阵列中的有缺陷的数据位而引起转向。

17. 发明授权

US07299374B2 Clock control method and apparatus for a memory array 有权
标题翻译：用于存储器阵列的时钟控制方法和装置
公开(公告)号：US07299374B2
公开(公告)日：2007-11-20
申请号：US11050580
申请日：2005-02-03
申请人： James W. Dawson , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
发明人： James W. Dawson , Paul A. Bunce , Donald W. Plass , Kenneth J. Reyer
IPC分类号： G06F1/08 , G06F1/04
CPC分类号： G06F1/04 , G11C7/22 , G11C7/222 , G11C7/227
摘要： A clock control method and apparatus are provided employing a clock control circuit which generates an array clock for a memory array from a system clock and a reset control signal. The reset control signal is one of a plurality of input control signals to the clock control circuit. When the system clock is below a predefined frequency threshold, the reset control signal is an array tracking reset signal, wherein the active pulse width of the array clock is system clock frequency independent, and when the system clock is above the predefined frequency threshold, the reset control signal is a mid-cycle reset signal, meaning that the active pulse width of the array clock is system clock frequency dependent. A bypass signal is provided as a third input control signal, which when active causes the clock control circuit to output an array clock which mirrors the system clock.
摘要翻译：提供了一种时钟控制方法和装置，其采用从系统时钟和复位控制信号产生用于存储器阵列的阵列时钟的时钟控制电路。复位控制信号是到时钟控制电路的多个输入控制信号之一。当系统时钟低于预定频率阈值时，复位控制信号是阵列跟踪复位信号，其中阵列时钟的有效脉冲宽度是系统时钟频率无关的，当系统时钟高于预定频率阈值时，复位控制信号是中周期复位信号，意味着阵列时钟的有效脉冲宽度取决于系统时钟。提供旁路信号作为第三输入控制信号，当有效时，时钟控制电路输出反映系统时钟的阵列时钟。

18. 发明授权

US06728912B2 SOI cell stability test method 失效
标题翻译： SOI电池稳定性试验方法
公开(公告)号：US06728912B2
公开(公告)日：2004-04-27
申请号：US09833724
申请日：2001-04-12
申请人： James W. Dawson , Paul A. Bunce , Donald W. Plass
发明人： James W. Dawson , Paul A. Bunce , Donald W. Plass
IPC分类号： G11C2900
CPC分类号： G11C29/12 , G11C8/08 , G11C29/34
摘要： A method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, uses a reset test circuit with a wordline pulse width control circuit which can be implemented without performance impact and allows using unused silicon to minimize area usage impact and permits screening of integrated SOI memory array circuits for weak SOI cells using the test reset circuit to selectively change the wordline pulse width to a reduced time while the memory cell bit select and write signals turn off at normal times to stress the cell write margin. Further, during test, the word line pulse width can be extended by blocking the reset signal of the reset path test circuit to the word path to produce a longer than normal pulse width. In addition, during a test for normal operations the reset signal is allowed to pass through a pass gate multiplexer of the reset test circuit.
摘要翻译：用于测试SOI技术存储器电路（例如SRAM）中用于弱SOI单元的方法使用具有字线脉冲宽度控制电路的复位测试电路，该电路可以在没有性能影响的情况下实现，并允许使用未使用的硅来最小化区域使用影响并允许使用测试复位电路筛选用于弱SOI单元的集成SOI存储器阵列电路，以便在正常时间存储单元位选择和写入信号关断以压缩单元写入裕度时选择性地将字线脉冲宽度改变为减小的时间。此外，在测试期间，可以通过将复位路径测试电路的复位信号阻塞到字路径来延长字线脉冲宽度，以产生比正常脉冲宽度更长的字线。此外，在正常操作的测试期间，允许复位信号通过复位测试电路的通过门极复用器。

19. 发明授权

US08599642B2 Port enable signal generation for gating a memory array device output 有权
标题翻译：用于门控存储器阵列器件输出的端口使能信号生成
公开(公告)号：US08599642B2
公开(公告)日：2013-12-03
申请号：US12822021
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar J. Vora
IPC分类号： G11C8/18 , G06F1/04
CPC分类号： G06F1/10 , G11C11/419
摘要： A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.
摘要翻译：产生用于将存储器阵列数据门控到输出节点的动态端口使能信号的方法包括产生输入动态时钟信号的可编程前沿时钟信号导出; 产生所述输入动态时钟信号的可编程后沿时钟信号导出，其中所述前沿时钟信号导出和所述后沿时钟信号导出可相对于彼此独立地可编程; 以及利用静态输入使能信号选通产生的可编程前导和后沿时钟信号导出，以便产生端口使能信号，使得当非活动时，端口使能信号防止早期存储器阵列数据耦合到输出节点。

20. 发明申请

US20110320851A1 PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT 有权
标题翻译：端口使能信号生成用于获取存储器阵列设备输出
公开(公告)号：US20110320851A1
公开(公告)日：2011-12-29
申请号：US12822021
申请日：2010-06-23
申请人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
发明人： Paul A. Bunce , John D. Davis , Diana M. Henderson , Jigar Vora
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： G06F1/10 , G11C11/419
摘要： A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node.
摘要翻译：产生用于将存储器阵列数据门控到输出节点的动态端口使能信号的方法包括产生输入动态时钟信号的可编程前沿时钟信号导出; 产生所述输入动态时钟信号的可编程后沿时钟信号导出，其中所述前沿时钟信号导出和所述后沿时钟信号导出可相对于彼此独立地可编程; 以及利用静态输入使能信号选通产生的可编程前导和后沿时钟信号导出，以便产生端口使能信号，使得当非活动时，端口使能信号防止早期存储器阵列数据耦合到输出节点。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式