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11. 发明申请

US20160099240A1 INTEGRATED ELECTROSTATIC DISCHARGE (ESD) CLAMPING 有权
标题翻译：集成静电放电（ESD）钳位
公开(公告)号：US20160099240A1
公开(公告)日：2016-04-07
申请号：US14966688
申请日：2015-12-11
申请人： Weize Chen , Patrice M. Parris
发明人： Weize Chen , Patrice M. Parris
IPC分类号： H01L27/02 , H01L27/07 , H01L21/768 , H01L21/762 , H01L29/66 , H01L29/06
CPC分类号： H01L27/0259 , H01L21/76224 , H01L21/76895 , H01L27/027 , H01L27/0711 , H01L27/0722 , H01L29/0623 , H01L29/0649 , H01L29/0653 , H01L29/1083 , H01L29/1087 , H01L29/6625 , H01L29/66659 , H01L29/66681 , H01L29/78 , H01L29/7835
摘要： A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region.
摘要翻译：制造具有用于静电放电（ESD）保护的双极型晶体管的横向扩散的金属氧化物半导体（LDMOS）晶体管器件的方法包括：掺杂衬底以在衬底中形成LDMOS晶体管器件的体区，所述体区具有第一导电类型，在衬底中形成LDMOS晶体管器件的掺杂隔离区域，掺杂隔离区域具有第二导电类型并围绕其中设置体区的LDMOS晶体管器件的器件区域，形成基极接触所述基极接触区域设置在所述主体区域内并且具有所述第一导电类型，并且掺杂所述衬底以形成用于限定所述双极晶体管的集电极区域的掺杂隔离区域的隔离接触区域，以形成所述双极晶体管的集电极区域在衬底中的LDMOS晶体管器件的源极和漏极区域，并且形成双极性tr的发射极区域体内区域内的电阻。

12. 发明授权

US09099487B2 Zener diode devices and related fabrication methods 有权
标题翻译：齐纳二极管器件及相关制造方法
公开(公告)号：US09099487B2
公开(公告)日：2015-08-04
申请号：US14098194
申请日：2013-12-05
申请人： Weize Chen , Xin Lin , Patrice M. Parris
发明人： Weize Chen , Xin Lin , Patrice M. Parris
IPC分类号： H01L29/861 , H01L31/107 , H01L29/66 , H01L29/866
CPC分类号： H01L29/866 , H01L21/76224 , H01L29/0611 , H01L29/0649 , H01L29/0653 , H01L29/0688 , H01L29/0692 , H01L29/08 , H01L29/66106
摘要： Zener diode structures and related fabrication methods and semiconductor devices are provided. An exemplary semiconductor device includes first and second Zener diode structures. The first Zener diode structure includes a first region, a second region that is adjacent to the first region, and a third region adjacent to the first region and the second region to provide a junction that is configured to influence a first reverse breakdown voltage of a junction between the first region and the second region. The second Zener diode structure includes a fourth region, a fifth region that is adjacent to the fourth region, and a sixth region adjacent to the fourth region and the fifth region to provide a junction configured to influence a second reverse breakdown voltage of a junction between the fourth region and the fifth region, wherein the second reverse breakdown voltage and the first reverse breakdown voltage are different.
摘要翻译：提供齐纳二极管结构及相关制造方法和半导体器件。示例性半导体器件包括第一和第二齐纳二极管结构。第一齐纳二极管结构包括第一区域，与第一区域相邻的第二区域，以及与第一区域和第二区域相邻的第三区域，以提供被配置为影响第一区域的第一反向击穿电压第一区域和第二区域之间的连接处。第二齐纳二极管结构包括第四区域，与第四区域相邻的第五区域以及与第四区域和第五区域相邻的第六区域，以提供被配置为影响第二区域的第二反向击穿电压第四区域和第五区域，其中第二反向击穿电压和第一反向击穿电压不同。

13. 发明申请

US20140001594A1 SCHOTTKY DIODE WITH LEAKAGE CURRENT CONTROL STRUCTURES 有权
标题翻译：肖特基二极管与漏电流控制结构
公开(公告)号：US20140001594A1
公开(公告)日：2014-01-02
申请号：US13537299
申请日：2012-06-29
申请人： Weize Chen , Xin Lin , Patrice M. Parris
发明人： Weize Chen , Xin Lin , Patrice M. Parris
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L29/0692 , H01L29/417 , H01L29/66143
摘要： A Schottky diode includes a device structure having a central portion and a plurality of fingers. Distal portions of the fingers overlie leakage current control (LCC) regions. An LCC region is relatively narrow and deep, terminating in proximity to a buried layer of like polarity. Under reverse bias, depletion regions forming in an active region lying between the buried layer and the LCC regions occupy the entire extent of the active region and thereby provide a carrier depleted wall. An analogous depletion region occurs in the active region residing between any pair of adjacent fingers. If the fingers include latitudinal oriented fingers and longitudinal oriented fingers, depletion region blockades in three different orthogonal orientations may occur. The formation of the LCC regions may include the use of a high dose, low energy phosphorous implant using an LCC implant mask and the isolation structures as an additional hard mask.
摘要翻译：肖特基二极管包括具有中心部分和多个指状物的器件结构。手指的远端覆盖泄漏电流控制（LCC）区域。 LCC区域相对较窄和深，终止于类似极性的掩埋层附近。在反向偏压下，在位于掩埋层和LCC区域之间的有源区域中形成的耗尽区域占据有源区域的整个范围，从而提供载流子耗尽的壁。类似的耗尽区发生在驻留在任何一对相邻手指之间的有源区域中。如果手指包括纬向取向的指状物和纵向取向的指状物，则可能发生三个不同正交取向的耗尽区域封锁。 LCC区域的形成可以包括使用使用LCC植入物掩模的高剂量，低能量磷植入物，并且将隔离结构用作附加的硬掩模。

14. 发明申请

US20140001549A1 SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A RESISTOR CIRCUIT, AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有有源器件的半导体器件和驱动器电路以及通过电阻电路互连的隔离结构及其制造方法
公开(公告)号：US20140001549A1
公开(公告)日：2014-01-02
申请号：US13671506
申请日：2012-11-07
申请人： HUBERT M. BODE , Weize Chen , Richard J. De Souza , Patrice M. Parris
发明人： HUBERT M. BODE , Weize Chen , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L27/04 , H01L21/02
CPC分类号： H01L27/04 , H01L21/02381 , H01L21/761 , H01L27/0629 , H01L27/092 , H01L29/0653 , H01L29/0847 , H01L29/0869 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/66659 , H01L29/66689 , H01L29/7817 , H01L29/7835
摘要： Embodiments of semiconductor devices and driver circuits include a semiconductor substrate having a first conductivity type, an isolation structure (including a sinker region and a buried layer), an active device within a portion of the substrate contained by the isolation structure, and a resistor circuit. The buried layer is positioned below the top substrate surface, and has a second conductivity type. The sinker region extends between the top substrate surface and the buried layer, and has the second conductivity type. The active device includes a body region, which is separated from the isolation structure by a portion of the semiconductor substrate having the first conductivity type. The resistor circuit is connected between the isolation structure and the body region. The resistor circuit may include one or more resistor networks and, optionally, a Schottky diode and/or one or more PN diode(s) in series and/or parallel with the resistor network(s).
摘要翻译：半导体器件和驱动器电路的实施例包括具有第一导电类型的半导体衬底，隔离结构（包括沉陷区和掩埋层），由隔离结构包含的衬底的一部分内的有源器件，以及电阻器电路。掩埋层位于顶部衬底表面下方，并且具有第二导电类型。沉降片区域在顶部衬底表面和掩埋层之间延伸，并且具有第二导电类型。有源器件包括主体区域，其通过具有第一导电类型的半导体衬底的一部分与隔离结构分离。电阻电路连接在隔离结构和体区之间。电阻器电路可以包括一个或多个电阻器网络，以及可选地与电阻器网络串联和/或并联的肖特基二极管和/或一个或多个PN二极管。

15. 发明授权

US07773424B2 Circuit for and an electronic device including a nonvolatile memory cell and a process of forming the electronic device 有权
标题翻译：包括非易失性存储单元的电路和电子设备以及形成电子设备的过程
公开(公告)号：US07773424B2
公开(公告)日：2010-08-10
申请号：US12126069
申请日：2008-05-23
申请人： Weize Chen , Patrice M. Parris
发明人： Weize Chen , Patrice M. Parris
IPC分类号： G11C11/34
CPC分类号： G11C16/0441 , G11C16/10 , H01L27/11519 , H01L27/11521
摘要： A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The circuit can further include a second transistor having a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal. When changing the state of the memory cell, the second transistor can be active and no significant amount of charge carriers are transferred between the gate electrode of the first transistor and the active region of the first transistor. Other embodiments can include the electronic device itself and a process of forming the electronic device.
摘要翻译：用于非易失性存储单元的电路可以包括电荷变换端子和输出端子。电路还可以包括具有电浮置的栅电极的第一晶体管和包括载流电极的有源区，其中载流电极耦合到输出端。电路还可以包括具有第一电极和第二电极的第二晶体管，其中第一电极耦合到第一晶体管的栅电极，第二电极耦合到电荷改变端。当改变存储单元的状态时，第二晶体管可以是有效的，并且在第一晶体管的栅电极和第一晶体管的有源区之间不传输大量的电荷载流子。其他实施例可以包括电子设备本身和形成电子设备的过程。

16. 发明授权

US07700996B2 Tunable antifuse elements 有权
标题翻译：可调谐反熔丝元件
公开(公告)号：US07700996B2
公开(公告)日：2010-04-20
申请号：US12361944
申请日：2009-01-29
申请人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
发明人： Patrice M. Parris , Weize Chen , John M. McKenna , Jennifer H. Morrison , Moaniss Zitouni , Richard J. De Souza
IPC分类号： H01L29/94
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/11206 , H01L2924/0002 , Y10S438/981 , H01L2924/00
摘要： A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
摘要翻译：可调谐反熔断元件（102,202,204,504,952）包括具有形成在表面中的有源区域（106）的基板材料（101），栅电极（104），其至少部分位于有源区域（106）和设置在栅电极（104）和有源区（106）之间的电介质层（110）。电介质层（110）包括可调阶梯结构（127）。在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过电介质层（110）的电流路径以及在破裂区域（130）中电介质层（110）的破裂。电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

17. 发明授权

US09991356B2 Integrated circuits devices with counter-doped conductive gates 有权
公开(公告)号：US09991356B2
公开(公告)日：2018-06-05
申请号：US15246262
申请日：2016-08-24
申请人： Weize Chen , Richard J. de Souza , Md M. Hoque , Patrice M. Parris
发明人： Weize Chen , Richard J. de Souza , Md M. Hoque , Patrice M. Parris
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/78 , H01L29/66 , H01L21/28 , H01L29/06 , H01L27/092 , H01L21/8234
CPC分类号： H01L29/4933 , H01L21/28052 , H01L21/28105 , H01L21/823443 , H01L21/823842 , H01L27/0922 , H01L29/0653 , H01L29/4983 , H01L29/66477 , H01L29/66575 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.

18. 发明授权

US09899500B2 Method of fabricating a tunable schottky diode with depleted conduction path 有权
公开(公告)号：US09899500B2
公开(公告)日：2018-02-20
申请号：US14269825
申请日：2014-05-05
申请人： Weize Chen , Xin Lin , Patrice M. Parris
发明人： Weize Chen , Xin Lin , Patrice M. Parris
IPC分类号： H01L29/66 , H01L29/872 , H01L29/10 , H01L27/06 , H01L29/06 , H01L29/08
CPC分类号： H01L29/66893 , H01L27/0629 , H01L29/0619 , H01L29/0623 , H01L29/0653 , H01L29/0692 , H01L29/08 , H01L29/1066 , H01L29/107 , H01L29/66143 , H01L29/872
摘要： A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

19. 发明授权

US09236472B2 Semiconductor device with integrated breakdown protection 有权
标题翻译：具有集成故障保护的半导体器件
公开(公告)号：US09236472B2
公开(公告)日：2016-01-12
申请号：US13448994
申请日：2012-04-17
申请人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
发明人： Weize Chen , Hubert M. Bode , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/10
CPC分类号： H01L29/7823 , H01L21/2253 , H01L29/0626 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835
摘要： A device includes a semiconductor substrate having a first conductivity type, a device isolating region in the semiconductor substrate, defining an active area, and having a second conductivity type, a body region in the active area and having the first conductivity type, and a drain region in the active area and spaced from the body region to define a conduction path of the device, the drain region having the second conductivity type. The device isolating region and the body region are spaced from one another to establish a first breakdown voltage lower than a second breakdown voltage in the conduction path.
摘要翻译：一种器件包括具有第一导电类型的半导体衬底，半导体衬底中的器件隔离区，限定有源区，并具有第二导电类型，有源区中的体区，并具有第一导电类型，漏极区域，并且与身体区域间隔开以限定器件的导电路径，漏极区域具有第二导电类型。器件隔离区域和体区域彼此间隔开以建立低于导通路径中的第二击穿电压的第一击穿电压。

20. 发明授权

US09024380B2 Semiconductor device with floating RESURF region 有权
标题翻译：具有浮动RESURF区域的半导体器件
公开(公告)号：US09024380B2
公开(公告)日：2015-05-05
申请号：US13529589
申请日：2012-06-21
申请人： Weize Chen , Richard J. De Souza , Patrice M. Parris
发明人： Weize Chen , Richard J. De Souza , Patrice M. Parris
IPC分类号： H01L29/66 , H01L29/06 , H01L29/78
CPC分类号： H01L29/0692 , H01L29/0634 , H01L29/0653 , H01L29/66659 , H01L29/7835
摘要： A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap.
摘要翻译：一种器件包括半导体衬底，半导体衬底中的主体区域，具有第一导电类型，并且包括电荷载流子流过的沟道区域，半导体衬底中的漏极区域，具有第二导电类型，并与第二导电类型间隔开沿着第一横向尺寸的主体区域，具有第二导电类型的半导体衬底中的漂移区域，以及将漏极区域电耦合到沟道区域，以及在半导体衬底相邻的多个浮动缩小表面场（RESURF）区域具有第一导电类型的漂移区域，并且电荷载流子在由施加到漏极区域的电压产生的电场下漂移穿过漂移区域。多个浮动RESURF区域的相邻的浮动RESURF区域沿设备的第二横向尺寸彼此间隔开。

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