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11. 发明授权

US06538929B2 Semiconductor integrated circuit device, memory module and storage device 有权
标题翻译：半导体集成电路器件，存储器模块和存储器件
公开(公告)号：US06538929B2
公开(公告)日：2003-03-25
申请号：US09987189
申请日：2001-11-13
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C1604
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： A semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory while sharing a data bus, and utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. This volatile memory includes a volatile storage circuit for latching repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory. A fuse program circuit is not needed for the defect repair, but a defect which occurs after burn-in can be newly repaired so that the new defect can be repaired even after the packaging is formed over a circuit substrate.
摘要翻译：提供一种半导体集成电路装置，其包括中央处理单元，电可重新编程的非易失性存储器和易失性存储器，同时共享数据总线，并且利用非易失性存储器的存储信息来修复易失性存储器的缺陷。这种易失性存储器包括一个易失性存储电路，用于锁存修复信息以用冗余存储单元修复有缺陷的正常存储单元。非易失性存储器响应于初始化半导体集成电路器件的指令从其自身读出修复信息。响应于初始化指令，易失性存储电路锁存来自非易失性存储器的修复信息。缺陷修复不需要保险丝编程电路，但是可以重新修复在老化之后发生的缺陷，使得即使在电路基板上形成封装之后，也可以修复新的缺陷。

12. 发明授权

US06967888B2 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件，存储器模块，存储器件和半导体集成电路器件修复方法
公开(公告)号：US06967888B2
公开(公告)日：2005-11-22
申请号：US11046769
申请日：2005-02-01
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.
摘要翻译：为了提高修复LSI的缺陷的效率，提供了一种半导体集成电路装置，其包括中央处理单元，电可重新编程的非易失性存储器和易失性存储器，共享数据总线，其利用非易失性存储器的存储信息修复易失性存储器的缺陷。易失性存储器包括用于通过冗余存储单元来锁定用于修复有缺陷的正常存储单元的修复信息的易失性存储电路。非易失性存储器响应于指令初始化从其自身读出修复信息，并且易失性存储电路锁存修复信息。检测维修不需要保险丝编程电路，可以对修复后的故障进行新修复，即使在包装后也能修复新的缺陷。

13. 发明授权

US06542414B2 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device 有权
公开(公告)号：US06542414B2
公开(公告)日：2003-04-01
申请号：US10178217
申请日：2002-06-25
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C1604
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of an LSI, a semiconductor integrated circuit device is provided which includes a central processing unit, an electrically reprogrammable nonvolatile memory and a volatile memory, sharing a data bus, which utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. The volatile memory includes a volatile storage circuit for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction initialization, and the volatile storage circuit latches the repair information. A fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired even after packaging.

14. 发明授权

US06341090B1 Method for repairing semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件修复方法
公开(公告)号：US06341090B1
公开(公告)日：2002-01-22
申请号：US09497119
申请日：2000-02-03
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C700
CPC分类号： G11C16/06
摘要： To improve the efficiency for repairing a defect of a large-scale integrated circuit. A semiconductor integrated circuit device comprises, a central processing unit (10), an electrically reprogrammable nonvolatile memory (11) and a volatile memory (12, 13) while sharing a data bus (16), and utilizes the stored information of the nonvolatile memory so as to repair a defect of the volatile memory. This volatile memory includes a volatile storage circuit (12AR, 13AR) for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory. Any fuse program circuit is not needed for the detect repair, but a defect to occur after a burn-in can be newly repaired so that the new defect can be repaired even after the packaging over a circuit substrate.
摘要翻译：一种半导体集成电路装置，包括中央处理单元（10），电可再编程非易失性存储器（11）和易失性存储器（12,13），同时共享数据总线（16），并且利用所存储的非易失性存储器的信息来修复易失性存储器的缺陷。这种易失性存储器包括一个易失性存储电路（12AR，13AR），用于通过冗余存储器单元锁存用于修复有缺陷的正常存储单元的修复信息。非易失性存储器响应于初始化半导体集成电路器件的指令从其自身读出修复信息。响应于初始化指令，易失性存储电路锁存来自非易失性存储器的修复信息。任何保险丝编程电路不需要用于检测修复，但是可以重新修复在老化之后发生的缺陷，使得即使在电路基板上的封装之后也可以修复新的缺陷。

15. 发明授权

US06324103B2 Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device 有权
公开(公告)号：US06324103B2
公开(公告)日：2001-11-27
申请号：US09756233
申请日：2001-01-09
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C1604
CPC分类号： G11C7/08 , G11C7/20 , G11C7/22 , G11C11/406 , G11C11/40615 , G11C11/4072 , G11C11/4074 , G11C16/06 , G11C16/20 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/026 , G11C29/028 , G11C29/4401 , G11C29/50012 , G11C29/70 , G11C2029/0401 , G11C2029/1208
摘要： To improve the efficiency for repairing a defect of a large-scale integrated circuit. A semiconductor integrated circuit device comprises, a central processing unit (10), an electrically reprogrammable nonvolatile memory (11) and a volatile memory (12, 13) while sharing a dat bus (16), and utilizes the stored information of the nonvolatile memory so as to repair a defect of the volatile memory. This volatile memory includes volatile storage circuit (12AR, 13AR) for latching the repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory. Any fuse program circuit is not needed for the detect repair, but a defect to occur after a burn-in can be newly repaired so that the new defect can be repaired even after the packaging over a circuit substrate.

16. 发明授权

US06201733B1 Semiconductor integrated circuit device, memory module and storage device 有权
标题翻译：半导体集成电路器件，存储器模块和存储器件
公开(公告)号：US06201733B1
公开(公告)日：2001-03-13
申请号：US09435035
申请日：1999-11-05
申请人： Mitsuru Hiraki , Shoji Shukuri
发明人： Mitsuru Hiraki , Shoji Shukuri
IPC分类号： G11C1604
CPC分类号： G11C16/06
摘要： To improve the efficiency for repairing a defect of a large-scale integrated circuit, a semiconductor integrated circuit device is formed of, a central processing unit (10), an electrically reprogrammable nonvolatile memory (11) and a volatile memory (12, 13) while sharing a data bus (16), and utilizes stored information of the nonvolatile memory to repair a defect of the volatile memory. This volatile memory includes a volatile storage circuit (12AR, 13AR) for latching repair information for repairing a defective normal memory cell with a redundancy memory cell. The nonvolatile memory reads out the repair information from itself in response to an instruction to initialize the semiconductor integrated circuit device. In response to the initializing instruction, the volatile storage circuit latches the repair information from the nonvolatile memory. No fuse program circuit is not needed for the detect repair, and a defect which occurs after a burn-in can be newly repaired so that the new defect can be repaired, even after the packaging over a circuit substrate.
摘要翻译：为了提高修复大规模集成电路的缺陷的效率，半导体集成电路器件由中央处理单元（10），电可重新编程的非易失性存储器（11）和易失性存储器（12,13）构成，同时共享数据总线（16），并利用非易失性存储器的存储信息来修复易失性存储器的缺陷。这种易失性存储器包括一个易失性存储电路（12AR，13AR），用于通过冗余存储单元来锁定用于修复有缺陷的正常存储单元的修复信息。非易失性存储器响应于初始化半导体集成电路器件的指令从其自身读出修复信息。响应于初始化指令，易失性存储电路锁存来自非易失性存储器的修复信息。不需要保险丝编程电路进行检测修复，并且可以重新修复在老化之后发生的缺陷，使得即使在电路基板上的封装之后也可以修复新的缺陷。

17. 发明授权

US08222686B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US08222686B2
公开(公告)日：2012-07-17
申请号：US13097731
申请日：2011-04-29
申请人： Shoji Shukuri
发明人： Shoji Shukuri
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/34 , H01L21/28273 , H01L21/28282 , H01L23/535 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/1157 , H01L27/11573 , H01L29/42328 , H01L29/42344 , H01L29/42368 , H01L29/45 , H01L29/4975 , H01L29/513 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/792 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a nonvolatile memory cell which includes a semiconductor substrate, a first insulating film formed over the semiconductor substrate, a control electrode formed over the first insulating film, the first insulating film acting as a gate insulator for the control gate electrode, a second insulating film formed over the semiconductor substrate, and a memory gate electrode formed over the second insulating film and being adjacent to the control gate electrode, the second insulating film acting as a gate insulator for the memory gate electrode and featuring a non-conductive charge trap film, the control gate electrode having a different type conductivity than that of the memory gate electrode. A manufacturing technique for a semiconductor device including a nonvolatile memory cell having control gate and memory gate electrodes is also featured.
摘要翻译：一种具有非易失性存储单元的半导体器件，包括半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的控制电极，用作控制栅电极的栅极绝缘体的第一绝缘膜，形成在所述半导体衬底上的第二绝缘膜，以及形成在所述第二绝缘膜上并与所述控制栅电极相邻的存储栅电极，所述第二绝缘膜用作所述存储栅电极的栅极绝缘体，并且具有非导电电荷所述控制栅电极具有与所述存储栅电极不同的导电类型。还提出了一种包括具有控制栅极和存储栅电极的非易失性存储单元的半导体器件的制造技术。

18. 发明申请

US20120112265A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件
公开(公告)号：US20120112265A1
公开(公告)日：2012-05-10
申请号：US13350703
申请日：2012-01-13
申请人： Natsuo AJIKA , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo AJIKA , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

19. 发明申请

US20100149875A1 Nonvolatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100149875A1
公开(公告)日：2010-06-17
申请号：US12714750
申请日：2010-03-01
申请人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
发明人： Natsuo Ajika , Shoji Shukuri , Masaaki Mihara , Yoshiki Kawajiri
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06
CPC分类号： G11C16/3436
摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.
摘要翻译：非易失性半导体存储器技术领域本发明涉及非易失性半导体存储器，更具体地说涉及具有增加的程序吞吐量的非易失性半导体存储器本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

20. 发明申请

US20090090961A1 Non-Volatile Semiconductor Memory Device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090090961A1
公开(公告)日：2009-04-09
申请号：US12246193
申请日：2008-10-06
申请人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
发明人： Natsuo Ajika , Shoji Shukuri , Satoshi Shimizu , Taku Ogura
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11568 , G11C16/0441 , G11C16/0491 , H01L21/26586 , H01L29/792
摘要： A non-volatile semiconductor device includes an n type well formed in a semiconductor substrate having a surface, the surface having a plurality of stripe shaped grooves and a plurality of stripe shaped ribs, a plurality of stripe shaped p type diffusion regions formed in upper parts of each of the plurality of ribs, the plurality of stripe shaped p type diffusion regions being parallel to a longitudinal direction of the ribs, a tunneling insulation film formed on the grooves and the ribs, a charge storage layer formed on the tunneling insulating film, a gate insulation film formed on the charge storage layer, and a plurality of stripe shaped conductors formed on the gate insulating film, the plurality of stripe shaped conductors arranged in a direction intersecting the longitudinal direction of the ribs with a predetermined interval wherein an impurity diffusion structure in the ribs are asymmetric.
摘要翻译：非易失性半导体器件包括在具有表面的半导体衬底中形成的n型阱，表面具有多个条形槽和多个条状肋，多个条形p型扩散区形成在上部所述多个条状p型扩散区域与所述肋的长度方向平行，形成在所述槽和所述肋上的隧道绝缘膜，形成在所述隧道绝缘膜上的电荷存储层，形成在电荷存储层上的栅极绝缘膜和形成在栅极绝缘膜上的多个条状导体，所述多个条状导体沿着与肋的纵向相交的方向以预定间隔布置，其中杂质扩散肋骨中的结构是不对称的。

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