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11. 发明授权

US07296208B2 Method and system for generating parallel decodable low density parity check (LDPC) codes 有权
标题翻译：用于产生并行解码低密度奇偶校验（LDPC）码的方法和系统
公开(公告)号：US07296208B2
公开(公告)日：2007-11-13
申请号：US10882705
申请日：2004-07-01
申请人： Feng-Wen Sun , Mustafa Eroz , Lin-Nan Lee
发明人： Feng-Wen Sun , Mustafa Eroz , Lin-Nan Lee
IPC分类号： H03M13/11
CPC分类号： H03M13/1168 , H03M13/1137 , H03M13/1165 , H03M13/6505
摘要： An approach is provided for efficiently decoding low density parity check (LDPC) codes. An LDPC decoder includes a memory for storing a mapped matrix that satisfies a plurality of parallel decodable conditions for permitting a lumped memory structure. Additionally, the decoder includes a parallel processors accessing edge values from the stored mapped matrix decode the LDPC codes. The above approach has particular applicability to satellite broadcast systems.
摘要翻译：提供了一种用于有效解码低密度奇偶校验（LDPC）码的方法。 LDPC解码器包括存储器，用于存储满足用于允许集中存储器结构的多个并行可解码条件的映射矩阵。此外，解码器包括从存储的映射矩阵访问边缘值的并行处理器解码LDPC码。上述方法对卫星广播系统具有特别的适用性。

12. 发明授权

US07260159B2 Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying (QPSK) or offset quaternary phase shift keying (OQPSK) 有权
标题翻译：用于提供与四相相移键控（QPSK）或偏移四相相移键控（OQPSK）向后兼容的更高阶调制的方法和装置，
公开(公告)号：US07260159B2
公开(公告)日：2007-08-21
申请号：US10142703
申请日：2002-05-10
申请人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
发明人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
IPC分类号： H03D3/22 , H04L27/22
CPC分类号： H04L27/3488 , H04L27/183
摘要： A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.
摘要翻译：提供一种提供能够被QPSK和OQPSK接收机以及PSK和QAM接收机解码的不对称向后兼容通信信号的方法和装置。本发明包括耦合到第一位流的定时误差累加器。第一比特流包括对于QPSK / OQPSK接收机和PSK / QAM接收机是共同的内容。相位误差累加器被耦合到第二比特流并且调整第二比特流中的符号的相位。相位和定时误差补偿器耦合到相位误差累加器和定时误差累加器，并调整从相位误差累加器和定时误差累加器接收的第一和第二比特流，以减少定时和相位误差。还提供耦合到相位和定时误差补偿器的高阶调制器。高阶调制器处理第一和第二比特流以提供不对称的向后兼容信号。

13. 发明授权

US07191378B2 Method and system for providing low density parity check (LDPC) encoding 有权
标题翻译：提供低密度奇偶校验（LDPC）编码的方法和系统
公开(公告)号：US07191378B2
公开(公告)日：2007-03-13
申请号：US10613823
申请日：2003-07-03
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/00 , G11C29/00
CPC分类号： H04L1/005 , H03M13/09 , H03M13/11 , H03M13/1102 , H03M13/1111 , H03M13/112 , H03M13/1137 , H03M13/1165 , H03M13/118 , H03M13/15 , H03M13/152 , H03M13/25 , H03M13/255 , H03M13/2906 , H03M13/356 , H03M13/6325 , H03M13/6583 , H04H40/90 , H04L1/0041 , H04L1/0057 , H04L1/006 , H04L1/0061 , H04L1/0065 , H04L1/0071 , H04L25/067 , H04L27/18 , H04L27/186 , H04L27/20 , H04L27/34 , H04L27/36
摘要： An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.
摘要翻译：提供了一种编码结构低密度奇偶校验（LDPC）码的方法。在编码处理期间访问表示低密度奇偶校验（LDPC）码的结构奇偶校验矩阵的存储器存储信息。该信息以表格形式组织，其中每行代表奇偶校验矩阵的一组列的第一列内的一个值的出现。这些行对应于奇偶校验矩阵的列组，其中根据预定操作导出每个组内的后续列。基于存储的表示奇偶校验矩阵的信息，输出LDPC编码信号。

14. 发明授权

US08140931B2 Method and system for generating parallel decodable low density parity check (LDPC) codes 有权
标题翻译：用于产生并行解码低密度奇偶校验（LDPC）码的方法和系统
公开(公告)号：US08140931B2
公开(公告)日：2012-03-20
申请号：US11938095
申请日：2007-11-09
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/1165 , H03M13/1137
摘要： An approach is provided for efficiently decoding low density parity check (LDPC) codes. A plurality of parallel processors decode the LDPC codes mapped by accessing a mapped matrix in a memory structure. The mapped matrix is constructed based on a parity check matrix of the LDPC codes. No two different entries in an identical row of the mapped matrix connects to identical bit nodes or identical check nodes.
摘要翻译：提供了一种用于有效解码低密度奇偶校验（LDPC）码的方法。多个并行处理器通过访问存储器结构中的映射矩阵来解码映射的LDPC码。基于LDPC码的奇偶校验矩阵构造映射矩阵。映射矩阵的相同行中没有两个不同的条目连接到相同的位节点或相同的校验节点。

15. 发明授权

US07954036B2 Method and system for providing low density parity check (LDPC) encoding 有权
标题翻译：提供低密度奇偶校验（LDPC）编码的方法和系统
公开(公告)号：US07954036B2
公开(公告)日：2011-05-31
申请号：US12195512
申请日：2008-08-21
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/00
CPC分类号： H04L1/005 , H03M13/09 , H03M13/11 , H03M13/1102 , H03M13/1111 , H03M13/112 , H03M13/1137 , H03M13/1165 , H03M13/118 , H03M13/15 , H03M13/152 , H03M13/25 , H03M13/255 , H03M13/2906 , H03M13/356 , H03M13/6325 , H03M13/6583 , H04H40/90 , H04L1/0041 , H04L1/0057 , H04L1/006 , H04L1/0061 , H04L1/0065 , H04L1/0071 , H04L25/067 , H04L27/18 , H04L27/186 , H04L27/20 , H04L27/34 , H04L27/36
摘要： An approach is provided for a method of encoding structure Low Density Parity Check (LDPC) codes. Memory storing information representing a structured parity check Matrix of Low Density Parity Check (LDPC) codes is accessed during the encoding process. The information is organized in tabular form, wherein each row represents occurrences of one Values within a first column of a group of columns of the parity check matrix. The rows correspond to groups of columns of the parity check matrix, wherein subsequent columns within each of the groups are derived according to a predetermined operation. An LDPC coded signal is output based on the stored information representing the parity check matrix.
摘要翻译：提供了一种编码结构低密度奇偶校验（LDPC）码的方法。在编码处理期间访问表示低密度奇偶校验（LDPC）码的结构化奇偶校验矩阵的存储器存储信息。信息以表格形式组织，其中每行代表奇偶校验矩阵的一组列的第一列内的一个值的出现。这些行对应于奇偶校验矩阵的列组，其中根据预定操作导出每个组内的后续列。基于存储的表示奇偶校验矩阵的信息，输出LDPC编码信号。

16. 发明申请

US20110047435A1 METHOD AND SYSTEM FOR PROVIDING SHORT BLOCK LENGTH LOW DENSITY PARITY CHECK (LDPC) CODES 有权
标题翻译：用于提供短块长度低密度奇偶校验（LDPC）编码的方法和系统
公开(公告)号：US20110047435A1
公开(公告)日：2011-02-24
申请号：US12706686
申请日：2010-02-16
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/29 , G06F11/10
CPC分类号： H04L1/0065 , H03M13/1137 , H03M13/116 , H03M13/118 , H03M13/152 , H03M13/255 , H03M13/2906 , H04L1/0057 , H04L1/0071
摘要： An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a short LDPC code by shortening longer mother codes. The short LDPC code has an outer Bose Chaudhuri Hocquenghem (BCH) code. According to another aspect, for an LDPC code with code rate of ⅗ utilizing 8-PSK (Phase Shift Keying) modulation, an interleaver provides for interleaving bits of the output LDPC code by serially writing data associated with the LDPC code column-wise into a table and reading the data row-wise from right to left. The above approach has particular application in digital video broadcast services over satellite.
摘要翻译：提供了一种用于生成低密度奇偶校验（LDPC）码的方法。 LDPC编码器通过缩短较长的母码产生短的LDPC码。短LDPC码具有外部Bose Chaudhuri Hocquenghem（BCH）码。根据另一方面，对于利用8-PSK（相移键控）调制的码率为an的LDPC码，交织器通过串行地将与LDPC码相关联的数据串行地写入到从右到左逐行阅读数据。上述方法在卫星数字视频广播业务中具有特殊应用。

17. 发明申请

US20090158117A1 METHOD AND SYSTEM FOR PROVIDING LONG AND SHORT BLOCK LENGTH LOW DENSITY PARITY CHECK (LDPC) CODES 有权
标题翻译：用于提供长和短块长密度低密度奇偶校验（LDPC）码的方法和系统
公开(公告)号：US20090158117A1
公开(公告)日：2009-06-18
申请号：US12355694
申请日：2009-01-16
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1165 , H03M13/1137 , H03M13/152 , H03M13/2906
摘要： An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For 1/3 rate, the relevant parameters are as follows: q=120, nldpc=64,800, kldpc=nBCH=21600, kBCH=21408 (12 bit error correcting BCH). For 1/4 rate, the LDPC code has the following relevant parameters: q=135, nldpc=64,800, kldpc=nBCH=16200, kBCH=16008 (12 bit error correcting BCH). For 2/5 rate, the following parameters exist: q=108, nldpc=64800, kldpc=nBCH=25920, kBCH=25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.
摘要翻译：提供了一种用于生成低密度奇偶校验（LDPC）码的方法。 LDPC编码器生成具有外部Bose Chaudhuri Hocquenghem（BCH）码的LDPC码。对于1/3速率，相关参数如下：q = 120，nldpc = 64,800，kldpc = nBCH = 21600，kBCH = 21408（12位纠错BCH）。对于1/4速率，LDPC码具有以下相关参数：q = 135，nldpc = 64,800，kldpc = nBCH = 16200，kBCH = 16008（12位纠错BCH）。对于2/5速率，存在以下参数：q = 108，nldpc = 64800，kldpc = nBCH = 25920，kBCH = 25728（12位纠错BCH）。上述方法在卫星数字视频广播业务中具有特殊应用。

18. 发明授权

US07376883B2 Method and system for providing long and short block length low density parity check (LDPC) codes 有权
标题翻译：提供长和短块长度低密度奇偶校验（LDPC）码的方法和系统
公开(公告)号：US07376883B2
公开(公告)日：2008-05-20
申请号：US10971509
申请日：2004-10-22
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/1165 , H03M13/1137 , H03M13/152 , H03M13/2906
摘要： An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For ⅓ rate, the relevant parameters are as follows: q=120, nldpc=64,800, kldpc=nBCH=21600, kBCH=21408 (12 bit error correcting BCH). For ¼ rate, the LDPC code has the following relevant parameters: q=135, nldpc=64,800, kldpc=nBCH=16200, kBCH=16008 (12 bit error correcting BCH). For ⅖ rate, the following parameters exist: q=108, nldpc=64800, kldpc=nBCH=25920, kBCH=25728 (12 bit error correcting BCH). The above approach has particular application in digital video broadcast services over satellite.
摘要翻译：提供了一种用于生成低密度奇偶校验（LDPC）码的方法。 LDPC编码器生成具有外部Bose Chaudhuri Hocquenghem（BCH）码的LDPC码。对于1/3速率，相关参数如下：q = 120，n×ldcc = 64,800，k ldpc = n BCH = 21600 ，BCH = 21408（12位纠错BCH）。对于¼速率，LDPC码具有以下相关参数：q = 135，n×ldcc = 64,800，k ldpc = n BCH = 16200 ，BCH = 16008（12位纠错BCH）。对于2/5速率，存在以下参数：q = 108，n×ldcc = 64800，k ldpc = n BCH = 25920，k BCH = 25728（12位纠错BCH）。上述方法在卫星数字视频广播业务中具有特殊应用。

19. 发明申请

US20070263751A1 Method and apparatus for providing higher order modulation that is backwards compatible with quaternary phase shift keying(QPSK) or offset quaternary phase shift keying (OQPSK) 有权
标题翻译：用于提供与四相相移键控（QPSK）或偏移四相相移键控（OQPSK）向后兼容的更高阶调制的方法和装置，
公开(公告)号：US20070263751A1
公开(公告)日：2007-11-15
申请号：US11879607
申请日：2007-07-18
申请人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
发明人： Lin-Nan Lee , Feng-Wen Sun , Mustafa Eroz , Yimin Jiang
IPC分类号： H03D3/22
CPC分类号： H04L27/3488 , H04L27/183
摘要： A method and apparatus for providing an asymmetrical backwards compatible communications signal that is capable of being decoded by QPSK and OQPSK receivers as well as PSK and QAM receivers is provided. The invention comprises a timing error accumulator coupled to a first bit stream. The first bit stream includes content that is common to the QPSK/OQPSK receiver and to the PSK/QAM receiver. A phase error accumulator is coupled to a second bit stream and adjusts the phase of symbols in the second bit stream. A phase and timing error compensator is coupled to the phase error accumulator and the timing error accumulator and adjusts the first and second bit streams received from the phase error accumulator and the timing error accumulator in order to reduce timing and phase errors. A higher order modulator coupled to the phase- and timing error compensator is also provided. The higher order modulator processes the first and second bit streams to provide the asymmetrical backwards compatible signal.
摘要翻译：提供一种提供能够被QPSK和OQPSK接收机以及PSK和QAM接收机解码的不对称向后兼容通信信号的方法和装置。本发明包括耦合到第一位流的定时误差累加器。第一比特流包括对于QPSK / OQPSK接收机和PSK / QAM接收机是共同的内容。相位误差累加器被耦合到第二比特流并且调整第二比特流中的符号的相位。相位和定时误差补偿器耦合到相位误差累加器和定时误差累加器，并调整从相位误差累加器和定时误差累加器接收的第一和第二比特流，以减少定时和相位误差。还提供耦合到相位和定时误差补偿器的高阶调制器。高阶调制器处理第一和第二比特流以提供不对称的向后兼容信号。

20. 发明申请

US20070226578A1 Method and apparatus for providing reduced memory low density parity check (LDPC) codes 有权
公开(公告)号：US20070226578A1
公开(公告)日：2007-09-27
申请号：US11805616
申请日：2007-05-24
申请人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
发明人： Mustafa Eroz , Feng-Wen Sun , Lin-Nan Lee
IPC分类号： H03M13/00
CPC分类号： H03M13/255 , H03M13/118 , H03M13/2906
摘要： An approach is provided for generating Low Density Parity Check (LDPC) codes. An LDPC encoder generates a LDPC code with an outer Bose Chaudhuri Hocquenghem (BCH) code. For a rate 3/5 code, the approach provides a degree profile that yields reduced memory requirements for storage of the edge values without significantly affecting the performance with respect to an “unmodified” rate 3/5 code. The relevant parameters for the reduced memory LDPC codes are as follows: q=72, nldpc=64800, kldpc=nBCH=38880, kBCH=38688. The above approach has particular application in digital video broadcast services over satellite.

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