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11. 发明授权

US06054872A Semiconductor integrated circuit with mixed gate array and standard cell 失效
标题翻译：具有混合门阵列和标准单元的半导体集成电路
公开(公告)号：US06054872A
公开(公告)日：2000-04-25
申请号：US997035
申请日：1997-12-23
申请人： Nobuo Fudanuki , Toshikazu Sei
发明人： Nobuo Fudanuki , Toshikazu Sei
IPC分类号： H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1735
摘要： The present invention relates to a semicustom ASIC, in which a plurality of standard cell rows are arranged. The standard cell and basic cells used in a gate array are mixedly mounted on the same chip. Respective cell rows are composed of a plurality of standard cells with an empty space. The basic cells used in the gate array are arranged as dummy cells. They are disposed in wiring channel regions between the plurality of standard cells or empty spaces between the standard cells in a same standard cell row. Only the latter may be used if the channelless type standard cells are employed. A changing request can be satisfied by forming metal wiring layers on the gate array basic cells when there is a necessity of changing circuit design or pattern. Since the circuit can be modified without change of gate polysilicon regions and source/drain regions underlying the metal wiring layers, design and manufacture can be effected in a short period of time.
摘要翻译：本发明涉及一种半定制ASIC，其中布置有多个标准单元行。门阵列中使用的标准单元和基本单元混合安装在同一芯片上。各个单元行由具有空白空间的多个标准单元组成。门阵列中使用的基本单元被布置为虚拟单元。它们被布置在同一标准单元行中的标准单元之间的多个标准单元之间的布线沟道区域或空白空间中。如果采用无通道型标准电池，则只能使用后者。当需要改变电路设计或图案时，可以通过在栅极阵列基本单元上形成金属布线层来满足变化的要求。由于可以在不改变栅极多晶硅区域和金属布线层下面的源极/漏极区域的情况下修改电路，因此可以在短时间内实现设计和制造。

12. 发明申请

US20060082404A1 Semiconductor integrated circuit with a logic circuit including a data holding circuit 有权
标题翻译：具有包括数据保持电路的逻辑电路的半导体集成电路
公开(公告)号：US20060082404A1
公开(公告)日：2006-04-20
申请号：US11245616
申请日：2005-10-07
申请人： Chihiro Ishii , Toshikazu Sei
发明人： Chihiro Ishii , Toshikazu Sei
IPC分类号： H03K3/356
CPC分类号： H03K3/0375 , H03K3/356156 , H03K3/356173
摘要： A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.
摘要翻译：半导体集成电路包括第一数据保持部，第一上拉电路，第一下拉电路，第一反馈电路和第二反馈电路。第一数据保持部保存第一输出数据。第一个上拉电路将输入数据作为上拉控制信号，当上拉控制信号取一个值时，拉起第一个输出数据。第一个下拉电路将输入数据作为下拉控制信号，当下拉控制信号取另一个值时，拉下第一个输出数据。第一反馈电路将对应于第一输出数据的第一反馈信号作为上拉控制信号反馈到第一上拉电路。第二反馈电路将与第一输出数据对应的第二反馈信号作为下拉控制信号反馈到第一下拉电路。

13. 发明授权

US06844630B2 Semiconductor integrated circuit device and wiring arranging method thereof 失效
公开(公告)号：US06844630B2
公开(公告)日：2005-01-18
申请号：US10081109
申请日：2002-02-25
申请人： Shinsuke Sakamoto , Yasuo Inbe , Masakazu Yaginuma , Kazunari Horikawa , Toshikazu Sei
发明人： Shinsuke Sakamoto , Yasuo Inbe , Masakazu Yaginuma , Kazunari Horikawa , Toshikazu Sei
IPC分类号： H01L21/82 , H01L21/00 , H01L23/50 , H01L23/48
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/15173 , H01L2924/00
摘要： Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.

14. 发明授权

US5614842A Semiconductor integrated circuit with buffer circuit and manufacturing method thereof 失效
标题翻译：具有缓冲电路的半导体集成电路及其制造方法
公开(公告)号：US5614842A
公开(公告)日：1997-03-25
申请号：US522962
申请日：1995-09-01
申请人： Katsuro Doke , Toshikazu Sei , Yasunobu Umemoto , Eiji Ban
发明人： Katsuro Doke , Toshikazu Sei , Yasunobu Umemoto , Eiji Ban
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/0948
CPC分类号： H03K19/0013
摘要： A semiconductor integrated circuit with a buffer circuit is disclosed. The source of the first P(N)MOS transistor is connected to a voltage supply (ground), its drain being connected to an output terminal. The source of the first N(P)MOS transistor is connected to the ground (voltage supply), its drain being connected to the output terminal. The gate of the second P(N)MOS transistor is connected to the gate of the first NMOS transistor, its source being connected to the voltage supply (ground) and its drain being connected to the output terminal. The gate of the second N(P)MOS transistor is connected to the gate of the first PMOS transistor, at least one of its source and drain being floated. A controller responses to an enable signal and an input signal to apply control signals to the gates of the first PMOS and NMOS transistors. By these control signals, any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is on. Whereas both the first PMOS and NMOS transistors are turned off irrespective of the input signal level when the enable signal is off. The semiconductor integrated circuit further includes an input buffer connected the output terminal via a resistor. The input buffer applies a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
摘要翻译：公开了一种具有缓冲电路的半导体集成电路。第一P（N）MOS晶体管的源极连接到电压源（地），其漏极连接到输出端子。第一N（P）MOS晶体管的源极连接到地（电源），其漏极连接到输出端。第二P（N）MOS晶体管的栅极连接到第一NMOS晶体管的栅极，其源极连接到电压源（地），其漏极连接到输出端子。第二N（P）MOS晶体管的栅极连接到第一PMOS晶体管的栅极，其源极和漏极中的至少一个浮动。控制器响应于使能信号和输入信号，以将控制信号施加到第一PMOS和NMOS晶体管的栅极。通过这些控制信号，当使能信号为接通时，基于输入信号电平，第一PMOS和NMOS晶体管中的任何一个导通。尽管当使能信号关闭时，第一PMOS晶体管和NMOS晶体管都被切断，而与输入信号电平无关。半导体集成电路还包括经由电阻器连接输出端子的输入缓冲器。输入缓冲器将出现在输出端子处的信号施加到半导体集成电路的内部电路。

15. 发明授权

US5239216A Clamping circuit for preventing output driving transistor from deep saturation state 失效
标题翻译：从深度饱和状态预防输出驱动晶体管的钳位电路
公开(公告)号：US5239216A
公开(公告)日：1993-08-24
申请号：US825130
申请日：1992-01-24
申请人： Toshikazu Sei , Yasunori Tanaka
发明人： Toshikazu Sei , Yasunori Tanaka
IPC分类号： H03K17/04 , H03K17/0422 , H03K17/567 , H03K17/615 , H03K17/66 , H03K19/08 , H03K19/173
CPC分类号： H03K17/0422
摘要： A semiconductor integrated circuit includes a current source for supplying a current i, a resistor, a switch having a control end connected to the resistor, an output terminal connected to the output end of the switch, a comparator having a current path which is connected at one end to a connection node between the resistor and the control end of the switch and connected at the other end to the output terminal. The comparator compares a voltage (i.times.R) occurring across the resistor with a potential V of the output terminal and permits the current i to flow into the output terminal when the relation (i.times.R.gtoreq.V) is attained.

16. 发明授权

US07446581B2 Semiconductor integrated circuit with a logic circuit including a data holding circuit 有权
标题翻译：具有包括数据保持电路的逻辑电路的半导体集成电路
公开(公告)号：US07446581B2
公开(公告)日：2008-11-04
申请号：US11245616
申请日：2005-10-07
申请人： Chihiro Ishii , Toshikazu Sei
发明人： Chihiro Ishii , Toshikazu Sei
IPC分类号： H03K3/356
CPC分类号： H03K3/0375 , H03K3/356156 , H03K3/356173
摘要： A semiconductor integrated circuit includes a first data holding section, a first pull-up circuit, a first pull-down circuit, a first feedback circuit, and a second feedback circuit. The first data holding section holds first output data. The first pull-up circuit takes in input data as a pull-up control signal and, when the pull-up control signal takes one value, pulls up the first output data. The first pull-down circuit takes in the input data as a pull-down control signal and, when the pull-down control signal takes the other value, pulls down the first output data. The first feedback circuit feeds back a first feedback signal corresponding to the first output data as the pull-up control signal to the first pull-up circuit. The second feedback circuit feeds back a second feedback signal corresponding to the first output data as the pull-down control signal to the first pull-down circuit.
摘要翻译：半导体集成电路包括第一数据保持部，第一上拉电路，第一下拉电路，第一反馈电路和第二反馈电路。第一数据保持部保存第一输出数据。第一个上拉电路将输入数据作为上拉控制信号，当上拉控制信号取一个值时，拉起第一个输出数据。第一个下拉电路将输入数据作为下拉控制信号，当下拉控制信号取另一个值时，拉下第一个输出数据。第一反馈电路将对应于第一输出数据的第一反馈信号作为上拉控制信号反馈到第一上拉电路。第二反馈电路将与第一输出数据对应的第二反馈信号作为下拉控制信号反馈到第一下拉电路。

17. 发明授权

US06962868B2 Semiconductor integrated circuit device and wiring arranging method thereof 失效
标题翻译：半导体集成电路器件及其布线方法
公开(公告)号：US06962868B2
公开(公告)日：2005-11-08
申请号：US10879723
申请日：2004-06-30
申请人： Shinsuke Sakamoto , Yasuo Inbe , Masakazu Yaginuma , Kazunari Horikawa , Toshikazu Sei
发明人： Shinsuke Sakamoto , Yasuo Inbe , Masakazu Yaginuma , Kazunari Horikawa , Toshikazu Sei
IPC分类号： H01L21/82 , H01L21/00 , H01L23/50 , H01L21/4763
CPC分类号： H01L23/50 , H01L2924/0002 , H01L2924/15173 , H01L2924/00
摘要： Even where an I/O cell requiring good characteristics is alloted to an I/O slot corresponding to the uppermost standard pattern wiring, a pad can be connected to the I/O slot by forming rewiring in the chip outermost peripheral area.
摘要翻译：即使需要良好特性的I / O单元被分配给与最上面的标准图案布线对应的I / O槽，也可以通过在芯片最外周区域中重新布线来将焊盘连接到I / O槽。

18. 发明授权

US06885071B2 Semiconductor integrated circuit making use of standard cells 失效
标题翻译：半导体集成电路利用标准单元
公开(公告)号：US06885071B2
公开(公告)日：2005-04-26
申请号：US10688083
申请日：2003-10-16
申请人： Yasunobu Umemoto , Toshikazu Sei , Toshiki Morimoto , Hiroaki Suzuki
发明人： Yasunobu Umemoto , Toshikazu Sei , Toshiki Morimoto , Hiroaki Suzuki
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8238 , H01L27/02 , H01L27/04 , H01L27/092 , H01L27/118 , H01L29/76
CPC分类号： H01L27/11807 , H01L27/0211
摘要： A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.
摘要翻译：描述了能够以更高的封装密度和小尺寸的标准电池结构制造的半导体集成电路。在半导体集成电路中，衬底区域和源极区域被相邻标准单元以及位于分别从衬底区域的中心向内位移的公共接触区域共享。

19. 发明授权

US6093942A Semiconductor device with improved pad layout 失效
标题翻译：具有改善焊盘布局的半导体器件
公开(公告)号：US6093942A
公开(公告)日：2000-07-25
申请号：US305472
申请日：1999-05-06
申请人： Toshikazu Sei , Yasunobu Umemoto
发明人： Toshikazu Sei , Yasunobu Umemoto
IPC分类号： H01L21/60 , H01L23/485 , H01L27/118
CPC分类号： H01L24/06 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2924/01004 , H01L2924/01013 , H01L2924/01033 , H01L2924/14 , H01L2924/1433
摘要： First I/O signal pads are arranged along the periphery of a semiconductor chip except corner sections thereof at a first pitch, and second I/O signal pads and power supply pads are arranged in the corner sections of the semiconductor chip. In this case, the second I/O signal pads and the power supply pads are alternately arranged at the first pitch, and arrangement of the power supply pads are set so that the pads are located at fixed sites common to semiconductor chips. With this arrangement, the second I/O signal pads are arranged at a pitch wider than the first pitch.
摘要翻译：第一I / O信号焊盘沿着半导体芯片的外围以除了其第一节距的角部分布置，并且第二I / O信号焊盘和电源焊盘布置在半导体芯片的拐角部分中。在这种情况下，第二I / O信号焊盘和电源焊盘以第一间距交替布置，并且电源焊盘的布置被设置为使得焊盘位于半导体芯片共同的固定位置。利用这种布置，第二I / O信号焊盘以比第一间距更宽的间距布置。

20. 发明授权

US6075389A Operation speed measuring circuit and semiconductor device incorporating the same circuit 失效
标题翻译：运行速度测量电路和包含相同电路的半导体器件
公开(公告)号：US6075389A
公开(公告)日：2000-06-13
申请号：US522955
申请日：1995-09-01
申请人： Yasunobu Umemoto , Toshikazu Sei , Katsuro Doke , Eiji Ban
发明人： Yasunobu Umemoto , Toshikazu Sei , Katsuro Doke , Eiji Ban
IPC分类号： G01R31/28 , G01R31/30 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/13 , H03D3/00
CPC分类号： G01R31/3016 , H03K5/133
摘要： An operation speed measuring circuit measures a difference in propagation delay time between first and second path 2, 3 including logic gates connected in series and thus confirms that an element provided on a chip obtains a specified operation speed. This operation speed measuring circuit is so constructed as to be controllable by an input signal IN from one input terminal 1 and can be therefore disposed in such an area that the number of placeable terminals is restricted down to a small number. When this operation speed measuring circuit is provided with a power supply terminal independent of other circuits, constructions of other circuits can be independently designed. When the operation speed measuring circuit is disposed in the area independent of an intra-chip integrated circuit design area, a degree of freedom of designing other circuits is improved. This independent area is set in one of corner areas on the semiconductor chip that have hitherto been nothing but empty areas, the degree of freedom of designing the circuit is further improved.
摘要翻译：操作速度测量电路测量包括串联连接的逻辑门的第一和第二路径2,3之间的传播延迟时间差，从而确认芯片上提供的元件获得指定的操作速度。该操作速度测量电路被构造成可以通过来自一个输入端子1的输入信号IN来控制，并且因此能够被设置在可放置端子的数量被限制在少数的区域内。当该操作速度测量电路具有独立于其它电路的电源端子时，可独立地设计其它电路的结构。当操作速度测量电路被设置在与片内集成电路设计区域无关的区域中时，提高了设计其他电路的自由度。这个独立区域被设置在半导体芯片的一个角区域中，迄今为止只是空白区域，电路设计的自由度进一步提高。

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