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1. 发明授权

US5614842A Semiconductor integrated circuit with buffer circuit and manufacturing method thereof 失效
标题翻译：具有缓冲电路的半导体集成电路及其制造方法
公开(公告)号：US5614842A
公开(公告)日：1997-03-25
申请号：US522962
申请日：1995-09-01
申请人： Katsuro Doke , Toshikazu Sei , Yasunobu Umemoto , Eiji Ban
发明人： Katsuro Doke , Toshikazu Sei , Yasunobu Umemoto , Eiji Ban
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/0948
CPC分类号： H03K19/0013
摘要： A semiconductor integrated circuit with a buffer circuit is disclosed. The source of the first P(N)MOS transistor is connected to a voltage supply (ground), its drain being connected to an output terminal. The source of the first N(P)MOS transistor is connected to the ground (voltage supply), its drain being connected to the output terminal. The gate of the second P(N)MOS transistor is connected to the gate of the first NMOS transistor, its source being connected to the voltage supply (ground) and its drain being connected to the output terminal. The gate of the second N(P)MOS transistor is connected to the gate of the first PMOS transistor, at least one of its source and drain being floated. A controller responses to an enable signal and an input signal to apply control signals to the gates of the first PMOS and NMOS transistors. By these control signals, any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is on. Whereas both the first PMOS and NMOS transistors are turned off irrespective of the input signal level when the enable signal is off. The semiconductor integrated circuit further includes an input buffer connected the output terminal via a resistor. The input buffer applies a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
摘要翻译：公开了一种具有缓冲电路的半导体集成电路。第一P（N）MOS晶体管的源极连接到电压源（地），其漏极连接到输出端子。第一N（P）MOS晶体管的源极连接到地（电源），其漏极连接到输出端。第二P（N）MOS晶体管的栅极连接到第一NMOS晶体管的栅极，其源极连接到电压源（地），其漏极连接到输出端子。第二N（P）MOS晶体管的栅极连接到第一PMOS晶体管的栅极，其源极和漏极中的至少一个浮动。控制器响应于使能信号和输入信号，以将控制信号施加到第一PMOS和NMOS晶体管的栅极。通过这些控制信号，当使能信号为接通时，基于输入信号电平，第一PMOS和NMOS晶体管中的任何一个导通。尽管当使能信号关闭时，第一PMOS晶体管和NMOS晶体管都被切断，而与输入信号电平无关。半导体集成电路还包括经由电阻器连接输出端子的输入缓冲器。输入缓冲器将出现在输出端子处的信号施加到半导体集成电路的内部电路。

2. 发明授权

US6075389A Operation speed measuring circuit and semiconductor device incorporating the same circuit 失效
标题翻译：运行速度测量电路和包含相同电路的半导体器件
公开(公告)号：US6075389A
公开(公告)日：2000-06-13
申请号：US522955
申请日：1995-09-01
申请人： Yasunobu Umemoto , Toshikazu Sei , Katsuro Doke , Eiji Ban
发明人： Yasunobu Umemoto , Toshikazu Sei , Katsuro Doke , Eiji Ban
IPC分类号： G01R31/28 , G01R31/30 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/13 , H03D3/00
CPC分类号： G01R31/3016 , H03K5/133
摘要： An operation speed measuring circuit measures a difference in propagation delay time between first and second path 2, 3 including logic gates connected in series and thus confirms that an element provided on a chip obtains a specified operation speed. This operation speed measuring circuit is so constructed as to be controllable by an input signal IN from one input terminal 1 and can be therefore disposed in such an area that the number of placeable terminals is restricted down to a small number. When this operation speed measuring circuit is provided with a power supply terminal independent of other circuits, constructions of other circuits can be independently designed. When the operation speed measuring circuit is disposed in the area independent of an intra-chip integrated circuit design area, a degree of freedom of designing other circuits is improved. This independent area is set in one of corner areas on the semiconductor chip that have hitherto been nothing but empty areas, the degree of freedom of designing the circuit is further improved.
摘要翻译：操作速度测量电路测量包括串联连接的逻辑门的第一和第二路径2,3之间的传播延迟时间差，从而确认芯片上提供的元件获得指定的操作速度。该操作速度测量电路被构造成可以通过来自一个输入端子1的输入信号IN来控制，并且因此能够被设置在可放置端子的数量被限制在少数的区域内。当该操作速度测量电路具有独立于其它电路的电源端子时，可独立地设计其它电路的结构。当操作速度测量电路被设置在与片内集成电路设计区域无关的区域中时，提高了设计其他电路的自由度。这个独立区域被设置在半导体芯片的一个角区域中，迄今为止只是空白区域，电路设计的自由度进一步提高。

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