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11. 发明授权

US07970025B2 System and method for tuning adjusting the central frequency of a laser while maintaining frequency stabilization to an external reference 有权
标题翻译：用于调整激光器的中心频率的系统和方法，同时保持对外部参考的频率稳定
公开(公告)号：US07970025B2
公开(公告)日：2011-06-28
申请号：US12496954
申请日：2009-07-02
申请人： Jeffrey Livas , James I. Thorpe , Kenji Numata
发明人： Jeffrey Livas , James I. Thorpe , Kenji Numata
IPC分类号： H01S3/10
CPC分类号： H01S3/1398
摘要： A method and system for stabilizing a laser to a frequency reference with an adjustable offset. The method locks a sideband signal generated by passing an incoming laser beam through the phase modulator to a frequency reference, and adjusts a carrier frequency relative to the locked sideband signal by changing a phase modulation frequency input to the phase modulator. The sideband signal can be a single sideband (SSB), dual sideband (DSB), or an electronic sideband (ESB) signal. Two separate electro-optic modulators can produce the DSB signal. The two electro-optic modulators can be a broadband modulator and a resonant modulator. With a DSB signal, the method can introduce two sinusoidal phase modulations at the phase modulator. With ESB signals, the method can further drive the optical phase modulator with an electrical signal with nominal frequency Ω1 that is phase modulated at a frequency Ω2.
摘要翻译：一种用于将激光器稳定到具有可调偏移的频率参考的方法和系统。该方法锁定通过将入射激光束通过相位调制器而产生的边带信号为频率参考，并且通过改变输入到相位调制器的相位调制频率来调整相对于锁定边带信号的载波频率。边带信号可以是单边带（SSB），双边带（DSB）或电子边带（ESB）信号。两个单独的电光调制器可以产生DSB信号。两个电光调制器可以是宽带调制器和谐振调制器。利用DSB信号，该方法可以在相位调制器上引入两个正弦相位调制。使用ESB信号，该方法可以用具有标称频率的电信号进一步驱动光相位调制器，并且以频率ωgr相位调制OHgr; 2。

12. 发明申请

US20100182413A1 ENDOSCOPE APPARATUS AND METHOD 有权
标题翻译：内窥镜装置和方法
公开(公告)号：US20100182413A1
公开(公告)日：2010-07-22
申请号：US12689504
申请日：2010-01-19
申请人： Kenji Numata
发明人： Kenji Numata
IPC分类号： H04N7/18
CPC分类号： A61B1/05 , A61B1/00039 , A61B1/0005 , A61B1/00105
摘要： An endoscope apparatus includes: a reading unit which reads video data and control data from a recording medium, the recording medium containing the video data including a plurality of image data and the control data used to control a measurement operation; a measuring unit which performs the measurement operation on the basis of the image data of the video data read by the reading unit; and a control unit which controls the measuring unit on the basis of the control data read by the reading unit.
摘要翻译：内窥镜装置包括：读取单元，其从记录介质读取视频数据和控制数据，所述记录介质包含包含多个图像数据的视频数据和用于控制测量操作的控制数据; 测量单元，其基于由读取单元读取的视频数据的图像数据执行测量操作; 以及控制单元，其基于由读取单元读取的控制数据来控制测量单元。

13. 发明授权

US6141288A Semiconductor memory device allowing change of refresh mode and address switching method therewith 失效
标题翻译：允许更改刷新模式和地址切换方法的半导体存储器件
公开(公告)号：US6141288A
公开(公告)日：2000-10-31
申请号：US314028
申请日：1999-05-19
申请人： Kenji Numata , Masaki Ogihara
发明人： Kenji Numata , Masaki Ogihara
IPC分类号： G11C11/406 , G11C5/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/44 , G11C29/50 , G11C29/56 , H01L27/10 , G11C8/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C29/028 , G11C29/44 , G11C29/50 , G11C29/50016 , G11C5/00 , G11C5/06 , G11C7/1018 , G11C11/401
摘要： A semiconductor integrated circuit device is described. The semiconductor device includes a switching signal generator having an output terminal which outputs a switching signal to change refresh modes. The semiconductor device also includes a first address buffer having an output terminal which outputs a first address signal, a second address buffer having an output terminal which outputs a second signal, a decoder having a first input terminal which receives the first address signal and having a second input terminal, a sense amplifier controller having an input terminal, and a switch having a first input terminal which receives the switching signal, a second input terminal which receives the second address signal, a first output terminal which outputs the second address signal to the second input terminal of the decoder and a second output terminal which outputs the second address signal to the input terminal of the sense amplifier controller, the switch being controlled by the switching signal.
摘要翻译：描述半导体集成电路器件。半导体器件包括具有输出端子的开关信号发生器，该输出端子输出切换信号以改变刷新模式。半导体器件还包括具有输出第一地址信号的输出端的第一地址缓冲器，具有输出第二信号的输出端的第二地址缓冲器，具有接收第一地址信号并具有第一地址信号的第一输入端的解码器第二输入端，具有输入端的读出放大器控制器和具有接收切换信号的第一输入端的开关，接收第二地址信号的第二输入端，向第二输入端输出第二地址信号的第一输出端，所述解码器的第二输入端子和将所述第二地址信号输出到所述读出放大器控制器的输入端的第二输出端子，所述开关由所述开关信号控制。

14. 发明授权

US5812481A Semiconductor integrated circuit device allowing change of product specification and chip screening method therewith 失效
标题翻译：半导体集成电路器件允许改变产品规格和芯片筛选方法
公开(公告)号：US5812481A
公开(公告)日：1998-09-22
申请号：US683780
申请日：1996-07-16
申请人： Kenji Numata , Masaki Ogihara
发明人： Kenji Numata , Masaki Ogihara
IPC分类号： G11C11/406 , G11C5/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/44 , G11C29/50 , G11C29/56 , H01L27/10 , G11C8/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C29/028 , G11C29/44 , G11C29/50 , G11C29/50016 , G11C5/00 , G11C5/06 , G11C7/1018 , G11C11/401
摘要： A semiconductor memory device includes a buffer for outputting an address signal and a decoding circuit having an input for receiving the address signal. A switch electrically connects the buffer to the input of the decoding circuit if a refresh mode specifying signal specifies a first data refresh mode, and electrically disconnects the buffer from the input of the decoding circuit if the refresh mode specifying signal specifies a second data refresh mode different from the first data refresh mode. An activating/deactivating circuit activates the input of the decoding circuit if the refresh mode specifying signal specifies the first data refresh mode and deactivates the input of the decoding circuit if the refresh mode specifying signal specifies the second data refresh mode.
摘要翻译：半导体存储器件包括用于输出地址信号的缓冲器和具有用于接收地址信号的输入的解码电路。如果刷新模式指定信号指定第一数据刷新模式，则开关将缓冲器电连接到解码电路的输入，并且如果刷新模式指定信号指定第二数据刷新模式，则将缓冲器与解码电路的输入电断开与第一个数据刷新模式不同。如果刷新模式指定信号指定第一数据刷新模式，则激活/去激活电路激活解码电路的输入，并且如果刷新模式指定信号指定第二数据刷新模式，则解除电路的输入。

15. 发明授权

US5377152A Semiconductor memory and screening test method thereof 失效
标题翻译：半导体存储器及其筛选试验方法
公开(公告)号：US5377152A
公开(公告)日：1994-12-27
申请号：US978883
申请日：1992-11-19
申请人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
发明人： Natsuki Kushiyama , Tohru Furuyama , Kenji Numata
IPC分类号： G11C29/02 , G11C29/24 , G11C29/50 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/028 , G11C29/24 , G11C29/50 , G11C11/401 , G11C2029/5004 , G11C2029/5006
摘要： A semiconductor memory comprises a dynamic type memory cell array arranged to form a matrix and provided with word lines commonly connected to memory cells of respective columns and bit lines commonly connected to memory cells of respective rows, a dummy cell section having a first set of dummy word lines connected to respective complimentary bit line pairs of said memory cell array by way of respective first capacitances and a second set of dummy word lines connected to respective complementary bit line pairs of said memory cell array by way of respective second capacitances, a dummy word line potential control circuit capable of optionally controlling the mode of driving selected dummy word lines when said word lines of said memory cell array are activated and sense amplifiers connected to the respective complementary bit line pairs of said memory cell array for reading data from selected memory cells of the memory cell array onto the related bit line.
摘要翻译：半导体存储器包括动态型存储单元阵列，其布置成形成矩阵并且设置有通常连接到相应列的存储器单元的字线和共同连接到各行的存储单元的位线的虚拟单元部分，虚拟单元部分具有第一组虚拟通过相应的第一电容连接到所述存储单元阵列的相应互补位线对的字线和通过相应的第二电容连接到所述存储单元阵列的相应互补位线对的第二组虚拟字线，线电势控制电路，当所述存储单元阵列的所述字线被激活时，能够可选地控制驱动所选择的虚拟字线的模式，以及连接到所述存储单元阵列的相应互补位线对的读出放大器，用于从所选存储单元读取数据的存储单元阵列到相关位线上。

16. 发明授权

US08730313B2 Endoscope apparatus and method 有权
标题翻译：内窥镜装置及方法
公开(公告)号：US08730313B2
公开(公告)日：2014-05-20
申请号：US12689504
申请日：2010-01-19
申请人： Kenji Numata
发明人： Kenji Numata
IPC分类号： A62B1/04
CPC分类号： A61B1/05 , A61B1/00039 , A61B1/0005 , A61B1/00105
摘要： An endoscope apparatus includes: a reading unit which reads video data and control data from a recording medium, the recording medium containing the video data including a plurality of image data and the control data used to control a measurement operation; a measuring unit which performs the measurement operation on the basis of the image data of the video data read by the reading unit; and a control unit which controls the measuring unit on the basis of the control data read by the reading unit.
摘要翻译：内窥镜装置包括：读取单元，其从记录介质读取视频数据和控制数据，所述记录介质包含包含多个图像数据的视频数据和用于控制测量操作的控制数据; 测量单元，其基于由读取单元读取的视频数据的图像数据执行测量操作; 以及控制单元，其基于由读取单元读取的控制数据来控制测量单元。

17. 发明申请

US20130308663A1 APPARATUS AND METHOD TO ENABLE PRECISION AND FAST LASER FREQUENCY TUNING 有权
标题翻译：使用精度和快速激光频率调谐的装置和方法
公开(公告)号：US20130308663A1
公开(公告)日：2013-11-21
申请号：US13474053
申请日：2012-05-17
申请人： JEFFREY R. CHEN , Kenji Numata , Stewart T. Wu , Guangning Yang
发明人： JEFFREY R. CHEN , Kenji Numata , Stewart T. Wu , Guangning Yang
IPC分类号： H01S3/10
CPC分类号： H01S5/06256 , G01S7/484 , H01S3/1304 , H01S3/1305 , H01S5/0687
摘要： An apparatus and method is provided to enable precision and fast laser frequency tuning. For instance, a fast tunable slave laser may be dynamically offset-locked to a reference laser line using an optical phase-locked loop. The slave laser is heterodyned against a reference laser line to generate a beatnote that is subsequently frequency divided. The phase difference between the divided beatnote and a reference signal may be detected to generate an error signal proportional to the phase difference. The error signal is converted into appropriate feedback signals to phase lock the divided beatnote to the reference signal. The slave laser frequency target may be rapidly changed based on a combination of a dynamically changing frequency of the reference signal, the frequency dividing factor, and an effective polarity of the error signal. Feed-forward signals may be generated to accelerate the slave laser frequency switching through laser tuning ports.
摘要翻译：提供了一种能够实现精确和快速的激光频率调谐的装置和方法。例如，使用光锁相环可以将快速可调的从属激光器动态地偏置锁定到参考激光线。从属激光器与参考激光线进行外差，以产生随后频率分频的节拍。可以检测分割的拍子和参考信号之间的相位差，以产生与相位差成比例的误差信号。误差信号被转换成适当的反馈信号，以将分频的beatnote锁定到参考信号。可以基于参考信号的动态变化的频率，分频因子和误差信号的有效极性的组合来快速地改变从属激光频率目标。可以产生前馈信号，以通过激光调谐端口加速从属激光器频率切换。

18. 发明授权

US07058863B2 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US07058863B2
公开(公告)日：2006-06-06
申请号：US10131194
申请日：2002-04-25
申请人： Toshiyuki Kouchi , Makoto Takahashi , Kenji Numata
发明人： Toshiyuki Kouchi , Makoto Takahashi , Kenji Numata
IPC分类号： G11C29/00
CPC分类号： H01L27/0203 , G11C5/025 , H01L27/10897 , H01L27/118
摘要： A semiconductor integrated circuit including a region of a memory macro function block is divided into memory core function block and interface function block regions. The interface function block includes a test circuit, a command decoder for a test, an address decoder for the test, a memory core input/output circuit which inputs a command and address into the memory core function block and transmits!receives data with the memory core function block, a configuration memory block in which information of a memory capacity of the memory core function block and configuration of a memory core is stored, and a configuration memory block which controls a data path and address path of the memory core function block based on the stored information.
摘要翻译：包括存储器宏功能块的区域的半导体集成电路被分为存储器核心功能块和接口功能块区域。接口功能块包括测试电路，用于测试的命令解码器，用于测试的地址解码器，存储器核心输入/输出电路，其将命令和地址输入到存储器核心功能块中并发送！与存储器接收数据核心功能块，其中存储有存储器核心功能块的存储器容量和存储器核心的配置的信息的配置存储器块，以及基于存储器核心功能块的数据路径和地址路径的配置存储器块对存储的信息。

19. 发明授权

US5970015A Semiconductor integrated circuit device allowing change of product specification and chip screening method therewith 失效
标题翻译：半导体集成电路器件允许改变产品规格和芯片筛选方法
公开(公告)号：US5970015A
公开(公告)日：1999-10-19
申请号：US102627
申请日：1998-06-23
申请人： Kenji Numata , Masaki Ogihara
发明人： Kenji Numata , Masaki Ogihara
IPC分类号： G11C11/406 , G11C5/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/408 , G11C29/00 , G11C29/44 , G11C29/50 , G11C29/56 , H01L27/10 , G11C8/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C29/028 , G11C29/44 , G11C29/50 , G11C29/50016 , G11C5/00 , G11C5/06 , G11C7/1018 , G11C11/401
摘要： A semiconductor integrated circuit device capable of changing the product specification. The semiconductor integrated circuit device includes an integrated circuit section containing a first circuit section having a first function and a second circuit section having a second function, and an active signal generator means for producing an active signal for activating the first circuit section or the second circuit section. To change the product specification, the integrated circuit device further includes a receiving for taking in a decision signal for determining the product specification a, switching signal generator, connected to the receiving device, for producing a switching signal for changing the product specification based on the decision signal, and switching device which receives the active signal and the switching signal, and which, based on the switching signal, changes the supply of the active signal to either the first circuit section or to the second circuit section.
摘要翻译：能够改变产品规格的半导体集成电路装置。半导体集成电路器件包括集成电路部分，其包含具有第一功能的第一电路部分和具有第二功能的第二电路部分;以及主动信号发生器装置，用于产生用于激活第一电路部分或第二电路的有效信号部分。为了改变产品规格，集成电路装置还包括用于接收用于确定产品规格a的判定信号的接收，连接到接收装置的切换信号发生器，用于产生用于基于所述接收装置改变产品规格的切换信号决定信号和接收有源信号和切换信号的开关装置，并且基于开关信号将有源信号的供给改变为第一电路部分或第二电路部分。

20. 发明授权

US5754481A Clock synchronous type DRAM with latch 失效
标题翻译：时钟同步型DRAM带锁存器
公开(公告)号：US5754481A
公开(公告)日：1998-05-19
申请号：US857559
申请日：1997-05-16
申请人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
发明人： Tomoaki Yabe , Kenji Numata , Katsuhiko Sato , Ryo Haga , Shinji Miyano , Tohru Furuyama
IPC分类号： G11C7/10 , G11C11/407 , G11C7/00
CPC分类号： G11C7/1006 , G11C7/1051 , G11C7/106 , G11C7/1072 , G11C7/1078
摘要： A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.
摘要翻译：半导体存储器件包括存储单元阵列，行解码器，位线对，读出放大器，读出放大器控制电路，数据锁存器，传输门，传输门控制电路和写电路。存储单元阵列具有以阵列形式排列的动态存储单元。行解码器解码行地址信号以选择存储单元阵列的所需行中的一行。每个位线对连接到布置在存储单元阵列的相应列上的存储单元的每一个。读出放大器放大在配对位线上读出的数据，并将数据反馈给配对的位线以保存数据。读出放大器控制电路控制读出放大器的工作。数据锁存器锁存读出数据和写入数据。传输门在数据锁存器和读出放大器之间传送数据。传输门控制电路控制传输门。写入电路与时钟信号同步地将数据写入数据锁存器。在将数据写入存储器单元时，数据预先由写入电路提供给数据锁存器并锁存在数据锁存器中，并且在传输门控制电路控制传输门以向位线对提供数据之后数据锁存器，读出放大器控制电路激活读出放大器。

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